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You said thqt ir_in is an input to my design and ir_out is the output from my design. I don't understand. Why should ir_in connected to LED?
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You indicated you wanted to investigate the sld_virtual_jtag component. You can do that by simply instantiating it and wire it to the I/O on your board, eg. something like:
-- Virtual JTAG interface
u1: sld_virtual_jtag
generic map (
sld_auto_instance_index => "YES",
sld_instance_index => 0,
sld_ir_width => VIR_WIDTH,
sld_sim_action => "",
sld_sim_n_scan => 0,
sld_sim_total_length => 0,
lpm_type => "sld_virtual_jtag"
)
port map (
-- JTAG signals
tck => tck,
tms => tms,
tdo => tdio,
tdi => tdio,
-- Virtual instruction register
ir_in => vir_in,
ir_out => vir_out
);
led <= vir_in;
where VIR_WIDTH is the number of LEDs.
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Because my design is only to make 4 LED blinking by using 4 bit counter. And I use clock divider to slow the clock that will be fed to the counter. If ir_in is connected to LED, that means the virtual jtag will interfere the "original" design.
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That's a different design. In this design, if you want to use the JTAG interface to say load the initial count, or disable the counter, you have to ensure you cross clock domains from the JTAG interface clock to the 50MHz clock domain correctly.
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So far these are what I've done:
1. Make the original design with verilog and later generate a bdf(block diagram file)
2. Make the vji using megawizard. And only generate bdf file.
3. From this step on, I don't know what should I do. How should I connect the block of my design and virtual jtag block.
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Stop using BDF. Wire the parts up using Verilog. You will need to learn how to use the Modelsim simulator eventually, and its much easier if you stick with an HDL language.
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How could I know how much width of IR is needed?(page3 of virtual jtag megawizard)
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How do you know how wide a counter should be? Its just a port, you make it as wide as you decide you need it (within the limit of the IP; 24-bits I think for the IR width).
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What I know from the pdf you gave me, IR is to define to which data TDI and TDO should connect(though I don't understand that).
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IR is used as an 'instruction' register in the JTAG terminology. In this particular component, its just an output port. You can do with it what you like.
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Why Altera don't give tutorial about this issue? They only discuss theory and how to use the megawizard not how to apply the megawizard to our design.
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Yep, I understand your pain :)
Cheers,
Dave
Honored Contributor
