Communication PC-De0 Nano

Hi Chris,

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I'm also trying to communicate via my PC to the DE0-Nano via the current USB connection. I was aiming to do basically option# 3, but Terasic wouldn't provide me any schematics for how the FTDI chip is connected to the Cyclone IV.

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Look at the DE2 schematics. Basically the FTDI parallel interface is connected to a CPLD, and the CPLD is connected to the JTAG pins on the FPGA. The CPLD implements an FTDI FIFO to CPLD logic bridge, and the CPLD logic implements a byte-stream command parser. The UrJTAG project has the commands that the USB-Blaster uses, and the FTDI drivers can be used to send those commands. However, the connection to the logic internal to the FPGA still has to use the JTAG interface, i.e., you have to understand the Virtual JTAG component or the JTAG-to-Avalon-MM bridge.

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I'm now looking into the JTAG options. I'm curious about how I actually assign the pins for working with the JTAG? I noticed when I create a JTAG interface using the Qsys w/ NIOS I never have to make any assignments in the Pin planner.

I've tried to generate a vJTAG using the megafunction wizard, and I can get to the point where my block is created (I'm using the schematic entry), but I have no idea how I assign the pins. The JTAG pins are not available in the Pin Planner...Are they automatically connected somehow?

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The JTAG pins are automatically connected. Read the document I posted. The JTAG hub is a block of logic that Altera uses to share the JTAG pins. If you use the Virtual JTAG component and an SignalTap instance, they both use the JTAG pins, so the HUB is there to multiplex data between the logic.

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(I'm still very new to this JTAG stuff so I might be completed confused about how to work with it :-)

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No problem. Feel free to ask questions.

Cheers,

Dave