Communication PC-De0 Nano

Hello Dave,

I think I am really hopeless here with vji.

Have you already finished the tutorial already? Please finish it. I really need everyone's help.

I found an example about vji from pdf you gave. Here is the code:

module counter (clock, my_counter);

input clock;

output [3:0] my_counter;

reg [3:0] my_counter;

always @ (posedge clock)

if (load && e1dr) // decode logic: used to load the counter my_counter

my_counter <= tmp_reg;

else

my_counter <= my_counter + 1;

// Signals and registers declared for VJI instance

wire tck, tdi;

reg tdo;

wire cdr, eldr, e2dr, pdr, sdr, udr, uir, cir;

wire [1:0] ir_in;

// Instantiation of VJI

my_vji VJI_INST(

.tdo (tdo),

.tck (tck),

.tdi (tdi),

.tms(),

.ir_in(ir_in),

.ir_out(),

.virtual_state_cdr (cdr),

.virtual_state_e1dr(e1dr),

.virtual_state_e2dr(e2dr),

.virtual_state_pdr (pdr),

.virtual_state_sdr (sdr),

.virtual_state_udr (udr),

.virtual_state_uir (uir),

.virtual_state_cir (cir)

);

// Declaration of data register

reg [3:0] tmp_reg;

// Decode Logic Block

// Making some decode logic from ir_in output port of VJI

wire load = ir_in[1] && ~ir_in[0];

// Bypass used to maintain the scan chain continuity for

// tdi and tdo ports

bypass_reg <= tdi;

// Data Register Block

always @ (posedge tck)

if ( load && sdr )

tmp_reg <= {tdi, tmp_reg[3:1]};

// tdo Logic Block

always @ (tmp_reg[0] or bypass_reg)

if(load)

tdo <= tmp_reg[0];

else

tdo <= bypass_reg;

endmodule

I have questions about this example.

1. From the pdf, I can read that tck is the clock used for shifting the data in and out on the TDI and TD0 pins. In the example above, what is actually "always @ (posedge tck)"? What I don't understand is how it become a "clock"? It doesn't even wired to the "input clock" of "module counter". Is it just "automatically has the same clock as De0 nano has?

2. What does the following code mean?

if ( load && sdr )

tmp_reg <= {tdi, tmp_reg[3:1]};

Why is "tmp_reg[3:1]" instead of "tmp_reg[3:0]"? What is the value of "tmp_reg[0]" then?

I know that sdr will become 1 when DR scan shift operation occurs or tdi is valid.

Load will be 1 if ir_in[1] = 1 and ir_in[0] = 0. (Please correct me if I'm wrong)

3. What happens here?

always @ (tmp_reg[0] or bypass_reg)

if(load)

tdo <= tmp_reg[0]

else

tdo <= bypass_reg;

I take it that "tmp_reg[0] or bypass_reg" are values that changing. But it doesn't seems that "tmp_reg[0]" get value from anywhere.

Thank You Dave.

Gunardi

PS. please finish your tutorial. I do need it. Thank you for your effort so far.