about Spansion flash

All of the above mentioned assignments are design specific. They are derived from the PHY IC's timing specifications as well as the PCB board trace delays.

With regards to the timing error. There appears to be one data path failing. I'm going to upload a new version of the MAC shortly. The eCos guys have started using the MAC and have uncovered a few issues which I have repaired. In addition to those changes I will modify the code slightly to ease the timing on this failing path.

Jake

Hi Jake,

Thanks for the reply! May I ask which data path is failing? I tried to track the timing error of eth_rx_clk but i did not really know where should i look into.

The path that was failing was a hold timing path on register q1 in an instance of eth_dc_reg. I've spent some time on it and can't really figure out why the fitter isn't able to meet the hold timing requirement other than the timing constraints I've put in the SDC file are somewhat overkill. The instance that was failing was the "tx_start_dc_reg" instance inside of "eth_avalon_rxdma.v".

Anyway, I modified the logic slightly so that only one register output feeds the input the the failing register and it still fails.

Finally I just went into the Fitter Settings (Assignment->Settings->Fitter Settings) and changed the fitter seed from 3 to 4 and that fixed it. Quartus then did a completely different optimization and placement on the register feeding the failing register and it passed. For the moment I'm going to write this off unless it presents itself elsewhere in the future.

Jake

Hi Jake,

And may i ask how can you trace the timing error to the hold timing path on register q1 in an instance of eth_dc_reg? I do not know how to do it using timeQuest Analyzer.

If you open TimeQuest and run the "Top Failing Paths" report, it will show you the full hierarchical names of the failing path. You know it's a hold timing violation because TimeQuest tells you that.

Jake

Hi Jake,

Thanks for the quick reply! I will test that.

Hi Jake,

Since i want to add some video block to your reference design i am thinking of modifying the eth_test_top.v. One thing i do not understand is that why the clk_sopc needs to be generated by top_pll.

top_pll top_pll_inst(

.inclk0 (clk_100mhz[0] ),

.c0 (clk_sopc ),

.c2 (sram_clk )

);

clk_sopc and the clk_100mhz[0] have the same clock frequency and there is no clock phase shift. But if i do use clk_100mhz[0] as the input to the sopc system the ethernet does not work...

another thing is, as i understand the reset_n_sopc in the reset module is only needed for PHY reset. So for video block example i can simply use reset_n, right?

reset# (.CLKS_PER_SEC(100000000),

.RESET_PER_NS(1000000)) reset_sopc_inst(

.clk (clk_sopc ),

.reset_req (~reset_n ),

.reset_n (reset_n_sopc )

);

Well your simple post actually brings up a lot of questions.

1 - clk_100mhz[0] is a 100 MHz clock from the board. I typically put it through the PLL just to clean it up somewhat. That doesn't mean you couldn't use the raw clock without running it through the PLL. However, probably the reason everything fails for you is that the timing constraints are written for the PLL output and not the raw clock.

The reset module provides a reset to all of the FPGA firmware. It guarantees a clean synchronous reset to the firmware on power up. I never recommend using a raw board input for an asynchronous reset signal. It's too difficult to constrain. I prefer to provide a clean synchronous reset for each clock domain if possible.

Jake

Hi Jake,

And thank you so much for answering all of them!!

Hi,

i still could not get the spansion flash s29GL256N11TFI020 work on the stratix II GX audio video board. This flash is not in the list of tested flash memories and it did not work when using the AMD29LV128M series of flash as Presets. I also tried to use "custom" Presets,address width 24 bits, data width 16 bits, timing: setup 45 ns, wait 160 ns, hold 45 ns. But it did not work either. I wonder if somebody succeeded in getting it work on this board ... Thank you in advance!