about Spansion flash

Well your simple post actually brings up a lot of questions.

1 - clk_100mhz[0] is a 100 MHz clock from the board. I typically put it through the PLL just to clean it up somewhat. That doesn't mean you couldn't use the raw clock without running it through the PLL. However, probably the reason everything fails for you is that the timing constraints are written for the PLL output and not the raw clock.

The reset module provides a reset to all of the FPGA firmware. It guarantees a clean synchronous reset to the firmware on power up. I never recommend using a raw board input for an asynchronous reset signal. It's too difficult to constrain. I prefer to provide a clean synchronous reset for each clock domain if possible.

Jake