about Spansion flash

Hi Jake,

Since i want to add some video block to your reference design i am thinking of modifying the eth_test_top.v. One thing i do not understand is that why the clk_sopc needs to be generated by top_pll.

top_pll top_pll_inst(

.inclk0 (clk_100mhz[0] ),

.c0 (clk_sopc ),

.c2 (sram_clk )

);

clk_sopc and the clk_100mhz[0] have the same clock frequency and there is no clock phase shift. But if i do use clk_100mhz[0] as the input to the sopc system the ethernet does not work...

another thing is, as i understand the reset_n_sopc in the reset module is only needed for PHY reset. So for video block example i can simply use reset_n, right?

reset# (.CLKS_PER_SEC(100000000),

.RESET_PER_NS(1000000)) reset_sopc_inst(

.clk (clk_sopc ),

.reset_req (~reset_n ),

.reset_n (reset_n_sopc )

);