Forum Discussion
New ContributorLogic elements utilization in FPGA
Hello All,
I have an old design on cyclone 3 with Quartus 10 and the used logic elements (in ALMs) are 20k.
Now, I migrate exactly the same design to Quartus 21 also I changed the FPGA to Cyclone V and now the used logic elements (in ALMs) are 4k.
So the only changes are the FPGA from Cyclone 3 to V and the Quartus version from 10 to 21.
Why the used logic elements (in ALMs) reduced from 20k to 4k?
What could wrong happend? w
PS. no optimization is done for both Quartus project.
Hi Taha,
Yes, with a large software jump I would expect differences in the project. Be it ALM usage or place & route or timing performance.
This is because as the Quartus versions change the optimization algorithm also changes.
I would suggest to also check for nodes that have been synthesized away. If your design is small enough, you can see it in the netlist viewers. It is easier to check in the warning messages too. Check for the below warning message
"Warning (14320): Synthesized away node"
Regards,
Nurina
9 Replies
NurinaRegular Contributor
Hi,
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Best regards,
Nurina
- Nurina
Hello,
Have you checked for the tri-state nodes as mentioned in the warnings?
I'm not familiar with tri-state usage in Cyclone V, but here are some threads that you may find useful:
As for your PLL clock settings warning, here are some threads you may find useful. It just seems like there is issues with the constraints, I would suggest using derive_pll_clocks :
https://community.intel.com/t5/Programmable-Devices/How-to-deal-with-this-warning/td-p/76741
https://www.intel.com/content/www/us/en/support/programmable/articles/000074876.html
Regards,
Nurina
- Nurina
Hi Taha,
Yes, with a large software jump I would expect differences in the project. Be it ALM usage or place & route or timing performance.
This is because as the Quartus versions change the optimization algorithm also changes.
I would suggest to also check for nodes that have been synthesized away. If your design is small enough, you can see it in the netlist viewers. It is easier to check in the warning messages too. Check for the below warning message
"Warning (14320): Synthesized away node"
Regards,
Nurina
FvMSuper Contributor
Hi,
the basic point wasn't yet mentioned. Cyclone III (respectively IV or 10) LE is a completely different metric than Cyclone V ALM. Cyclone III LE has one 4-input LUT, ALM has two 6-input LUTs. Effectivity of 4- versus 6-input LUTs is different depending on the complexity of logic or arithmetic operations. Therefore it's difficult to define a general factor.
- Nurina
I'm not entirely sure. Have you checked for any logic/register that have been synthesized away? Is the design working as expected in simulation and hardware tests?
Regards,
Nurina
t_alarsThank you for quick reply @Nurina .
The total registers drop from 10k to 7k. I am still facing some issues with the testing however, I just want to know if I can consider this drop as normal.
Sure later on with simulation and test i will get the correct answer.
But for know, is this might be normal cuz we have 11 years gap between the Quartus version and the fpga used?
Cheers,
Taha
- Nurina
Hi,
This can happen when you change device or Quartus versions.
It could be that the device and Quartus version is better at optimizing this.
Regards,
Nurina
