Forum Discussion
Logic elements utilization in FPGA
- 2 years ago
Hi Taha,
Yes, with a large software jump I would expect differences in the project. Be it ALM usage or place & route or timing performance.
This is because as the Quartus versions change the optimization algorithm also changes.
I would suggest to also check for nodes that have been synthesized away. If your design is small enough, you can see it in the netlist viewers. It is easier to check in the warning messages too. Check for the below warning message
"Warning (14320): Synthesized away node"
Regards,
Nurina
Hello,
Have you checked for the tri-state nodes as mentioned in the warnings?
I'm not familiar with tri-state usage in Cyclone V, but here are some threads that you may find useful:
As for your PLL clock settings warning, here are some threads you may find useful. It just seems like there is issues with the constraints, I would suggest using derive_pll_clocks :
https://community.intel.com/t5/Programmable-Devices/How-to-deal-with-this-warning/td-p/76741
https://www.intel.com/content/www/us/en/support/programmable/articles/000074876.html
Regards,
Nurina