Forum Discussion
Logic elements utilization in FPGA
- 2 years ago
Hi Taha,
Yes, with a large software jump I would expect differences in the project. Be it ALM usage or place & route or timing performance.
This is because as the Quartus versions change the optimization algorithm also changes.
I would suggest to also check for nodes that have been synthesized away. If your design is small enough, you can see it in the netlist viewers. It is easier to check in the warning messages too. Check for the below warning message
"Warning (14320): Synthesized away node"
Regards,
Nurina
I'm not entirely sure. Have you checked for any logic/register that have been synthesized away? Is the design working as expected in simulation and hardware tests?
Regards,
Nurina
- t_alars2 years ago
New Contributor
Thank you for quick reply @Nurina .
The total registers drop from 10k to 7k. I am still facing some issues with the testing however, I just want to know if I can consider this drop as normal.
Sure later on with simulation and test i will get the correct answer.
But for know, is this might be normal cuz we have 11 years gap between the Quartus version and the fpga used?
Cheers,
Taha