Forum Discussion
Logic elements utilization in FPGA
- 2 years ago
Hi Taha,
Yes, with a large software jump I would expect differences in the project. Be it ALM usage or place & route or timing performance.
This is because as the Quartus versions change the optimization algorithm also changes.
I would suggest to also check for nodes that have been synthesized away. If your design is small enough, you can see it in the netlist viewers. It is easier to check in the warning messages too. Check for the below warning message
"Warning (14320): Synthesized away node"
Regards,
Nurina
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