HardSigmoid and Intel FPGA AI suite

Hi @JohnT_Intel

I'm sorry, but currently, I'm trying to understand Intel FPGA AI Suite documentation, get used to the workflow, and apply it to my own neural network, so maybe I'm a little confused.

At this moment, I'm not able to confirm whether this model can be run in an Intel FPGA AI Suite IP core. In the examples provided in the "Intel FPGA AI Suite: Getting Started Guide" and "Intel FPGA AI Suite SoC Design Example User Guide," the "--foutput-format=open_vino_hetero" option is used, and the model is run in a prebuilt core. I know this option makes the model run on both the CPU and FPGA, but I understand that only non-supported layers are run on the CPU.

The question is, why does the H-sigmoid layer, which should be compatible with Intel FPGA AI Suite according to the "Intel FPGA AI Suite IP Reference Manual," seems to be executed on the CPU after compiling the graph?

Hi @JohnT_Intel

Do you mean that the compiling and performance estimation process is different when using the Intel FPGA AI Suite compared to not using it?

Based on the information provided in the "Intel FPGA AI Suite: Getting Started Guide" and the "Intel FPGA AI Suite SoC Design Example User Guide," I understand that a license is needed to build the Intel FPGA AI Suite core IP bitstream, but compiling the graph does not require a license.

To test my own model without a license, can I compile it with the "A10_Performance.arch" files, as demonstrated in the examples, and test it with the prebuilt SD card image?

Hi @JohnT_Intel,

I'm sorry, but the "Intel FPGA AI Suite Compiler Reference Manual" in Chapter 3 explains how to obtain different performance and area estimations using the "dla_compiler" for a graph on a given architecture and how to optimize the architecture. However, it doesn't directly address my question regarding why the H-sigmoid layer appears to be implemented in software instead of hardware.

The issue may be related to the "--fplugin" parameter, which is optional. The documentation mentions that the typical value is "HETERO:FPGA,CPU," and I understand that I may be getting the same result without specifying it because I have layers implemented in both the CPU and FPGA, as shown in the screenshot from the first message, is that correct? I compiled the graph with "--fplugin HETERO:FPGA,CPU" and I got the same result.

Furthermore, it doesn't answer my question about how to test the model. I can obtain performance estimations correctly, but I'm still working on running the model in the FPGA AI Suite core IP.

Hello @JohnT_Intel,

I tried to compile the graph with several architectures from $COREDLA_ROOT/example_architectures/, but I get the same result. I attempted using A10/S10/AGX7_Generic/Performance.arch architecture files, and in none of them, H-Sigmoid is implemented in the FPGA. The "Intel FPGA AI Suite SoC Design Example User Guide" requires graph compilation with A10_performance.arch. It is understood that the bitstream must be compiled with that architecture file. However, I can't find any information in Intel's documentation regarding layer-architecture dependencies. In Intel FPGA AI Suite: IP Reference Manual Chapter 2.3, all the compatible layers are listed, but the architectures are not specified. That's why I'm asking; according to Intel documentation, the H-Sigmoid layer should be supported. could you confirm it?

Hello @JohnT_Intel ,

Which new release are you referring to? Is it a new release of Intel FPGA AI Suite?

Are there any specified changes that need to be made in the architecture files as mentioned in the Intel documentation?

AN933 is "Updating Intel® Stratix® 10 FPGA Firmware" and I am working with Intel Arria 10 FPGA.