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RubenPadial's avatar
RubenPadial
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3 years ago

HardSigmoid and Intel FPGA AI suite

Hello, I have a trained neural network with PyTorch. I exported it in ONNX format and successfully obtained the IR model using the OpenVino toolkit. The model includes a HardSiLU (or H-Swish) activa...
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JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Please refer to "fpga-ai-suite-compiler-reference-manual.pdf" Chapter 3.


  • RubenPadial's avatar
    RubenPadial
    Icon for Contributor rankContributor
    3 years ago

    Hi @JohnT_Intel,

    I'm sorry, but the "Intel FPGA AI Suite Compiler Reference Manual" in Chapter 3 explains how to obtain different performance and area estimations using the "dla_compiler" for a graph on a given architecture and how to optimize the architecture. However, it doesn't directly address my question regarding why the H-sigmoid layer appears to be implemented in software instead of hardware.

    The issue may be related to the "--fplugin" parameter, which is optional. The documentation mentions that the typical value is "HETERO:FPGA,CPU," and I understand that I may be getting the same result without specifying it because I have layers implemented in both the CPU and FPGA, as shown in the screenshot from the first message, is that correct? I compiled the graph with "--fplugin HETERO:FPGA,CPU" and I got the same result.

    Furthermore, it doesn't answer my question about how to test the model. I can obtain performance estimations correctly, but I'm still working on running the model in the FPGA AI Suite core IP.