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Re: Where is FreeRTOS-Plus-TCP Design
Hi SueC, I read the design file mentioned for A10 TSE + SGMII but found it's an old project using Quartus 16 without OS?? Now I found a driver for RGMII inside the BSP folder ../AlteraTSE/tse_driver Any suggestions on driver for SGMII/ MII. Thank you.14Views0likes0CommentsWhere is FreeRTOS-Plus-TCP Design
Hello, Can someone show or share me the link or design data regarding "FreeRTOS-Plus-TCP" mentioned in Nios V Processor SW Dev. HB? https://docs.altera.com/r/docs/743810/25.3.1/nios-v-processor-software-developer-handbook/enabling-freertos-plus-tc Thank you.39Views0likes5CommentsNios V on External Memory
Hi all, I am looking for support on Nios V executing on external memory. This is a customer board with C10 GX. The EMIF has been verified using the EMIF toolkit and the calibration report is fine. I followed the steps to have the Nios V booting from GSFI, execute from onchip_ram and it's fine. Now I change the settings of Linker Section Mapping to EMIF, Then it's not working anymore. Nios Vm connects to EMIF through an Avalon MM clock crossing bridge. And the Quartus version is Pro. 24.1.0 Any suggestions or comments? Thank you.917Views0likes4Comments