JLee25
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VVP RAM Clk
Hello, I am using VVP Pixels In Parallel converter Lite Mode, convert from parallel pixels from 4 to 2. Configurations see below. All the connections are fine and no error messages on Platform Designer. But failed to pass synthesis for errors like, clock connection.. How can I debug this issue? The project is running on Quartus Pro 25.3.0. Thank you.Nios V on External Memory
Hi all, I am looking for support on Nios V executing on external memory. This is a customer board with C10 GX. The EMIF has been verified using the EMIF toolkit and the calibration report is fine. I followed the steps to have the Nios V booting from GSFI, execute from onchip_ram and it's fine. Now I change the settings of Linker Section Mapping to EMIF, Then it's not working anymore. Nios Vm connects to EMIF through an Avalon MM clock crossing bridge. And the Quartus version is Pro. 24.1.0 Any suggestions or comments? Thank you.
