ContributionsMost RecentMost LikesSolutions...Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally - Fixed! When compiling DDR3 SDRAM Controller with UniPHY Intel® FPGA IP core with Platform Designer on Windows 10 with Quartus Lite 20.1. 1.720 I get the error: Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/20.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally My WIndows 11 machine does not produce this error. I have tried all the solutions for reinstalling WSL and Ubuntu-18.04 and setting WSL to version 1 by following all the related threads but the issue is the same. I even tried Quart Lite 23.1.1.993 but on Windows 10 its the same error. This used to work with Windows10 so I think a Windows 10 upgrade has caused this. Windows 10 Enterprise Version 22H2 OS build 19045.6159 -Finally fixed this by moving my project folder off the C: drive and into the Users directory. It must be a permissions thing. Re: altera_mem_if_ddr3_emif Is the issue that the MAX10 PLL doesnt have enough PLL outputs? Re: altera_mem_if_ddr3_emif If opening Platform designer with no Project selected , I see the 'half-rate' tick box in DDR3 SDRAM Controller with UniPHY Intel FPGA IP, regardless of Quartus version. If the project is for a MAX10, the tick box disappears and I have no afi_half_clk. I can find no explanation for this. altera_mem_if_ddr3_emif Hi altera_mem_if_ddr3_emif used to have a parameter box 'enable afi half rate clock' in Quartus 18 Somewhere between V18 and V23 it has disappeared and I cant get afi_half_clk to work any more. How do I enable afi_half_clk in V23? SolvedRe: NiosV No- first time I have seen that requirement! Disabling GSFI is only when using alt_load to run code from Flash. It has to be enabled for using bootloader running from RAM. However - the point is the hexfile has to be Big endian for NiosV conversion to .pof file. Nios2 had to be Little endian, that fixes it. First time I ever saw that!!! Its a major difference. AN978 never mentions such a difference. You can close this now. Thanks. Re: NiosV I inspected the QSPI signals on the board and all are moving. The clock is at the correct speed. Re: NiosV You are right , it doesnt execute from QSPI flash. So the issue isnt so much the bootloader, but the NiosV isnt reading QSPI Flash at all. Same software/hardware/ QSYS works with Nios2. Only difference is Nios2 swapped with NiosV. My Flash is Micron MT25QL256 and I use the quartus.ini pgm_allow_mt25q=on. I tried Niosv-m and Niosv-g. Neither seem to run from Flash. I am using Generic QUAD SPI controller II Intel FPGA IP which worked with Nios2 . Should I be using Generic Serial Flash Interface Intel FPGA IP as stated in the Embedded Design Handbook? Shouldnt have to. Re: NiosV Great! - I confirmed "niosv_g_bootloader.srec" works just fine when using UFM internal flash to store software. It doesnt work when using Generic QSPI. Interestingly I notice that Nios 2 had a number of bootloaders . I used the one for CFI flash. NiosV only has one for each version.Its not clear whether any of them support QSPI. This is my last problem. Give me an answer to this and I can close this issue! Re: NiosV Finally I have something that almost works. Use Ashling IDE 24.1.1 "import niosv cmake project" and build project. Downloading the elf file works either with Asling IDE 'Run as' or NiosV command shell niosv-download! It doesnt run from External Flash though I do know elf2flash and riscv32-unknown-elf-objcopy both commands work because I verified them with a nios2 elf I also get it working using internal flash for code storage and alt_load for writable sections. So that just leaves the "niosv_g_bootloader.srec" which replaced Nios2 "boot_loader_cfi.srec". Can we be certain "niosv_g_bootloader.srec" works with Generic QSPI?? Re: NiosV Nios2 with the same design works ok on Quartus 23.1.1.