altera_mem_if_ddr3_emif

If opening Platform designer with no Project selected , I see the 'half-rate' tick box in DDR3 SDRAM Controller with UniPHY Intel FPGA IP, regardless of Quartus version.
If the project is for a MAX10, the tick box disappears and I have no afi_half_clk.
I can find no explanation for this.

Is the issue that the MAX10 PLL doesnt have enough PLL outputs?

Hi NGord,

For Max 10 FPGA device, the DDR3 EMIF IP doesn't support afi half rate clk.

I think the Cyclone V device is used by default if no project is opened.

Therefore, the DDR3 EMIF IP is targeting to Cyclone V and you may see the afi half rate clock option.

Regards,

Adzim