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NGord's avatar
NGord
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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altera_mem_if_ddr3_emif

Hi altera_mem_if_ddr3_emif used to have a parameter box 'enable afi half rate clock' in Quartus 18 Somewhere between V18 and V23 it has disappeared and I cant get afi_half_clk to work a...
Memory
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    2 years ago

    Hi @NGord

    Do you have any further question in this thread?

    Regards,

    Adzim

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi NGord,


For Max 10 FPGA device, the DDR3 EMIF IP doesn't support afi half rate clk.

I think the Cyclone V device is used by default if no project is opened.

Therefore, the DDR3 EMIF IP is targeting to Cyclone V and you may see the afi half rate clock option.


Regards,

Adzim