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Re: Transceiver data corruption
Hi CheepinC_altera, Thanks for your note! I have indeed looked into this already. As far as I can tell, I think it must be an issue with the reset sequence, as the data does seem to loopback correctly every so often. This may indicate an issue with the CDR lock, right? Especially as signal taps reports that the on the TX parallel bus is as expected each time. I am hoping someone might notice what I have done differently enough from the reference designs to cause this intermittent issue. I have combed through both my design above and the reference design a few times and seem to keep missing whatever the key difference is. Many thanksTransceiver data corruption
I am trying to externally loopback a simple data-stream using the GTS on the Agilex 5, over an external QSFP loopback module. The GTS is configured as followed: External clock chip: Outputs 156.25 MHz clock verified using an oscilloscope. System PLL: Outputs 125 MHz to the GTS. GTS: Basic PMA Direct System PLL freq: 125 MHz PMA speed: 1250 Mbps PMA width: 10 TX/RX PLL/CDR: 156.25 MHz TX/RX core interface FIFO: single width TX/RX clock: System PLL clock /1 The RTL used to transfer data over TX: module top( input CPU_RESET_n, input REFCLK, output gts_o_tx_serial_data, output gts_o_tx_serial_data_n, input gts_i_rx_serial_data, input gts_i_rx_serial_data_n ); // gts logic gts_pma_cu_clk_i; logic gts_tx_reset, gts_rx_reset; logic gts_tx_reset_ack, gts_rx_reset_ack; logic gts_tx_ready, gts_rx_ready; logic tx_coreclkin, rx_coreclkin; (* noprune *) logic gts_tx_clkout, gts_rx_clkout; logic gts_rs_grant_i; logic gts_rc_rs_req_o; (* noprune *) logic gts_tx_pll_locked /* synthesis keep */; (* noprune *) logic gts_rx_is_lockedtodata /* synthesis keep */; (* noprune *) logic gts_rx_is_lockedtoref /* synthesis keep */; logic o_refclk2core; (* noprune *) logic [79:0] gts_i_tx_parallel_data /* synthesis keep */; (* noprune *) logic [79:0] gts_o_rx_parallel_data /* synthesis keep */; assign gts_pma_cu_clk_i = srcss_bank1_pma_cu_clk_o; assign tx_coreclkin = gts_tx_clkout; assign rx_coreclkin = gts_rx_clkout; assign gts_rs_grant_i = srcss_bank1_rs_grant_o; // reset sequencer signals logic srcss_bank1_rs_grant_o; logic srcss_bank1_rs_priority; logic srcss_bank1_rc_rs_req; logic srcss_bank1_pma_cu_clk_o; assign srcss_bank1_rs_priority = '0; assign srcss_bank1_rc_rs_req = gts_rc_rs_req_o; // system pll signals logic gts_systempll_refclk_rdy; assign gts_systempll_refclk_rdy = 1'b1; gts_top u0 ( // gts .gts_top_clock_bridge_rx_in_clk_clk (QSFP_REFCLK_p), .gts_top_clock_bridge_tx_in_clk_clk (QSFP_REFCLK_p), .intel_directphy_gts_0_i_pma_cu_clk_clk (gts_pma_cu_clk_i), .intel_directphy_gts_0_i_tx_reset_tx_reset (gts_tx_reset), .intel_directphy_gts_0_i_rx_reset_rx_reset (gts_rx_reset), .intel_directphy_gts_0_o_tx_reset_ack_tx_reset_ack (gts_tx_reset_ack), .intel_directphy_gts_0_o_rx_reset_ack_rx_reset_ack (gts_rx_reset_ack), .intel_directphy_gts_0_o_tx_ready_tx_ready (gts_tx_ready), .intel_directphy_gts_0_o_rx_ready_rx_ready (gts_rx_ready), .intel_directphy_gts_0_i_tx_coreclkin_clk (tx_coreclkin), .intel_directphy_gts_0_i_rx_coreclkin_clk (rx_coreclkin), .intel_directphy_gts_0_o_tx_clkout_clk (gts_tx_clkout), .intel_directphy_gts_0_o_rx_clkout_clk (gts_rx_clkout), .intel_directphy_gts_0_i_src_rs_grant_src_rs_grant (gts_rs_grant_i), .intel_directphy_gts_0_o_src_rs_req_src_rs_req (gts_rc_rs_req_o), .intel_directphy_gts_0_o_tx_serial_data_o_tx_serial_data (gts_o_tx_serial_data), .intel_directphy_gts_0_o_tx_serial_data_n_o_tx_serial_data_n (gts_o_tx_serial_data_n), .intel_directphy_gts_0_i_rx_serial_data_i_rx_serial_data (gts_i_rx_serial_data), .intel_directphy_gts_0_i_rx_serial_data_n_i_rx_serial_data_n (gts_i_rx_serial_data_n), .intel_directphy_gts_0_o_tx_pll_locked_o_tx_pll_locked (gts_tx_pll_locked), .intel_directphy_gts_0_o_rx_is_lockedtodata_o_rx_is_lockedtodata (gts_rx_is_lockedtodata), .intel_directphy_gts_0_o_rx_is_lockedtoref_o_rx_is_lockedtoref (gts_rx_is_lockedtoref), .intel_directphy_gts_0_o_refclk2core_o_refclk2core (o_refclk2core), .intel_directphy_gts_0_i_tx_parallel_data_i_tx_parallel_data (gts_i_tx_parallel_data), .intel_directphy_gts_0_o_rx_parallel_data_o_rx_parallel_data (gts_o_rx_parallel_data), // reset sequencer signals .intel_srcss_gts_0_o_src_rs_grant_src_rs_grant (srcss_bank1_rs_grant_o), .intel_srcss_gts_0_i_src_rs_priority_src_rs_priority (srcss_bank1_rs_priority), .intel_srcss_gts_0_i_src_rs_req_src_rs_req (srcss_bank1_rc_rs_req), .intel_srcss_gts_0_o_pma_cu_clk_clk (srcss_bank1_pma_cu_clk_o), // system pll signals .intel_systemclk_gts_0_i_refclk_rdy_data (gts_systempll_refclk_rdy) ); // syncronise reset logic gts_tx_system_reset; altera_reset_synchronizer #( .ASYNC_RESET (1), .DEPTH (2) ) gts_tx_rst_sync ( .reset_in (~CPU_RESET_n), .clk (gts_tx_clkout), .reset_out (gts_tx_system_reset) ); // generate test data stream logic [7:0] counter; logic [7:0] test_stream; always_ff @(posedge gts_tx_clkout or posedge gts_tx_system_reset) begin if (gts_tx_system_reset) begin counter <= 8'b0; test_stream <= 8'b0; end else begin counter <= counter + 1; case (counter) 8'd0: test_stream <= 8'h3C; 8'd1: test_stream <= 8'h7F; 8'd2: test_stream <= 8'h11; 8'd3: test_stream <= 8'h07; default: test_stream <= 8'h00; endcase end end // detect and transform idle data, and mark control symbols logic [7:0] idle_data_transform; logic control_symbol_detect; always_comb begin idle_data_transform = (test_stream == 8'h00) ? 8'hBC : test_stream; control_symbol_detect = (idle_data_transform == 8'h1C) || (idle_data_transform == 8'h3C) || (idle_data_transform == 8'h5C) || (idle_data_transform == 8'h7C) || (idle_data_transform == 8'h9C) || (idle_data_transform == 8'hBC) || (idle_data_transform == 8'hDC) || (idle_data_transform == 8'hFC) || (idle_data_transform == 8'hF7) || (idle_data_transform == 8'hFB) || (idle_data_transform == 8'hFD) || (idle_data_transform == 8'hFE); end // pipline combinational logic to ensure timings are met logic [7:0] idle_data_transform_r; logic control_symbol_detect_r; always_ff @ (posedge gts_tx_clkout or posedge gts_tx_system_reset) begin if(gts_tx_system_reset) begin idle_data_transform_r <= 8'b0; control_symbol_detect_r <= 1'b0; end else begin idle_data_transform_r <= idle_data_transform; control_symbol_detect_r <= control_symbol_detect; end end // --- 8b/10b Encoding --- // https://libsv.readthedocs.io/en/latest/encoder_8b10b.html logic [9:0] encoded_out; logic code_error; encoder_tx encoder_inst ( .i_clk (gts_tx_clkout), .i_reset_n (~gts_tx_system_reset), .i_en (1'b1), .i_8b (idle_data_transform_r), .i_ctrl (control_symbol_detect_r), .o_10b (encoded_out), .o_code_err (code_error) ); // pipeline encoded outputs to ensure timing is met logic [9:0] encoded_out_r; always_ff @(posedge gts_tx_clkout or posedge gts_tx_system_reset) begin if (gts_tx_system_reset) encoded_out_r <= 10'b0; else encoded_out_r <= encoded_out; end // send data over TX logic data_path_rdy_tx; always_ff @(posedge gts_tx_clkout or posedge gts_tx_system_reset) begin if (gts_tx_system_reset) begin gts_i_tx_parallel_data <= 80'b0; data_path_rdy_tx <= 0; end else begin data_path_rdy_tx <= gts_tx_ready && gts_tx_pll_locked; case (data_path_rdy_tx) 1: gts_i_tx_parallel_data <= {1'b1, 39'b0, 1'b0, 1'b1, 28'b0, encoded_out_r}; 0: gts_i_tx_parallel_data <= 80'b0; endcase end end endmodule This RTL passes timing standalone, but when signal tap is used, it does produce warnings. In SignalTap I take the following measurments: Instance TX: data: gts_i_tx_parallel_data[79:0] clock domain: gts_tx_clkout Instance RX: data: gts_i_rx_parallel_data[79:0] clock domain: gts_rx_clkout The issue I am seeing is intermitted failures upon bitstream-re-configure: On the TX side, after the encoder has encoded, the TX data reads as folowed: (EXPECTED): ... 283, 17C, 283, 17C, 183, 335, 0B1, 347, 283, 17C, 283, 17C, ... This is the expected pattern on the RX side (post-framing) However, in my experiments so far, I have found that it only sometimes works: Here are the framing results after 5 different re-flashes: (FAILURE): ... 283, 17C, 283, 17C, 383, 135, 0B1, 347, 083, 37C, 283, 17C, ... (FAILURE): ... 283, 17C, 283, 17C, 383, 135, 0B1, 347, 083, 37C, 283, 17C, ... (FAILURE): ... 283, 17C, 283, 17D, 183, 335, 0B1, 346, 283, 17C, 283, 17C, ... (SUCCESS): ... 283, 17C, 283, 17C, 183, 335, 0B1, 347, 283, 17C, 283, 17C, ... (FAILURE): ... 283, 17C, 283, 175, 1B1, 307, 083, 37C, 283, 17C, 283, 17C, ... If anyone has any idea of what else to try, it would be much appreciated!Agilex5 .sof programming error
Has anybody ever seen this error when trying to program a design with a .sof: CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A55/A76) Model: SoCFPGA Agilex5 Terasic Atum A5 DRAM: 2 GiB (effective 4 GiB) Core: 47 devices, 25 uclasses, devicetree: separate WDT: Not starting watchdog@10d00200 WDT: Not starting watchdog@10d00300 WDT: Not starting watchdog@10d00400 WDT: Not starting watchdog@10d00500 WDT: Not starting watchdog@10d00600 NAND: 0 MiB MMC: mmc0@10808000: 0 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... Loading Environment from UBI... "Synchronous Abort" handler, esr 0x96000010, far 0x108d2000 elr: 0000000080263ce8 lr : 0000000080263ef4 (reloc) elr: 00000000ffd54ce8 lr : 00000000ffd54ef4 x0 : 00000000108d2000 x1 : 0000000000003228 x2 : 00000000ff8f4d30 x3 : 0000000000003260 x4 : 0000000000004e3c x5 : 0000000000006320 x6 : 0000000000003234 x7 : 0000000000000001 x8 : 00000000ff8e8a70 x9 : 0000000000003228 x10: 00000000ff8e65ec x11: 0000000000000798 x12: 0000000000000000 x13: 00000000ff8e8a70 x14: 00000000ffffffff x15: 00000000ff8e643d x16: 00000000ffcfdb90 x17: 0000000000000000 x18: 00000000ff8eed90 x19: 00000000ff8f4d30 x20: 00000000ff8f1360 x21: 00000000ff8f12c0 x22: 00000000ff8fb3b0 x23: 0000000000000001 x24: 0000000000000000 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000ff8e6750 Code: 32000021 d5033fbf b9000001 d65f03c0 (b9400001) Resetting CPU ... ### ERROR ### Please RESET the board ### I am using this build flow for the OS, and the GHRD from CDROM v1.4.0 It is worth noting that when programming with the .jic generated by the same project using: quartus_pfg -c golden_top_hps.sof golden_top_hps.jic -o device=MT25QU512 -o flash_loader=A5ED065BB32AR0 -o mode=ASX4 There is no such issue. ThanksRe: Agilex 5 GTS to HPS CDC/STA issue: help request!
Hi I have discovered that replacing the line: .intel_directphy_gts_0_o_rx_parallel_data_o_rx_parallel_data (gts_o_rx_parallel_data) with .intel_directphy_gts_0_o_rx_parallel_data_o_rx_parallel_data (32'b0) Lets the system boot - based on this; what would you recommend?Re: Agilex 5 GTS to HPS CDC/STA issue: help request!
It is Quartus 24.3. Yes it is in HPS First mode. When executing the command you mentioned, I get this result: SOCFPGA_AGILEX5 # fpga load 0 ${fpgadata} ${fpgadatasize} .............................................................FPGA reconfiguration failed! Command 'load' failed: Error -110Re: Agilex 5 GTS to HPS CDC/STA issue: help request!
Hi - unfortunately with JTAG programming, this error occurs: ... Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... Loading Environment from UBI... "Synchronous Abort" handler, esr 0x96000010, far 0x108d2000 elr: 0000000080263ce8 lr : 0000000080263ef4 (reloc) elr: 00000000ffd54ce8 lr : 00000000ffd54ef4 x0 : 00000000108d2000 x1 : 0000000000003228 ... Code: 32000021 d5033fbf b9000001 d65f03c0 (b9400001) Resetting CPU ... ### ERROR ### Please RESET the board ### Here the u-boot and linux branches are: git clone -b atuma5_v1.1 https://github.com/terasic/u-boot-socfpga u-boot-socfpga git clone --filter=tree:0 -b atuma5_v1.2 https://github.com/terasic/linux-socfpga linux-socfpga It is worth also noting, that: 1: It seems doing it this way does let the bitstream load onto the FPGA (based on LED responses) 2: Doing it this way with a base HPS bitstream (with no GTS component) lets the boot sequence finish successfullyAgilex5: XVCR Toolkit
I am trying to use the XVCR Toolkit on the Atum A5 by following the user guide SPEC: In Section 3.7.2 the clock connections are defined: I am using PMA clocking, with a Phase Compensation FIFO and 2x Width transfer, which implies the use of o_tx/rx_clkout2, the Word clock and a 2x division factor. Table 61 also suggests we do not need custom cadence gen. In Section 3.9.6 the reset sequence is defined: Which implies this snippet should be used at the top level HDL: always @(posedge system_clk_100) begin if (system_reset) begin gts_i_tx_reset <= 1'b1; gts_i_rx_reset <= 1'b1; end else begin if((gts_o_tx_reset_ack==1'b1) && (gts_o_rx_reset_ack==1'b1)) begin gts_i_tx_reset <= 1'b0; gts_i_rx_reset <= 1'b0; end end end In Section 3.11.1, the JTAG connection to the GTS is defined: Which suggests to define the following snippet in the HPS definition: .intel_directphy_gts_0_reconfig_address (address_bridge[17:0]) DESIGN: All of this combines into the following GTS configuration and system definition: GTS PMA/FEC PHY settings changed from default: ------------------------------ Datapath clocking mode : PMA TX/RX PMA interface FIFO mode : Register TX/RX clock clock source : Word Clock Enable TX/RX_clkout2 port : YES TX/RX clkout_2 clock source : Word Clock TX/RX _clkout2 div by : 2 Enable Avalon Memory Mapped interface : YES Enable Direct PHY soft CSR : YES Enable Debug Ednpoint on Avalon interface : YES With the following Qsys connections, and top level RTL connections: module golden_top(...); ... // GTS signals reg gts_i_tx_reset, gts_i_rx_reset; wire gts_o_tx_reset_ack, gts_o_rx_reset_ack; wire gts_o_tx_clkout, gts_o_rx_clkout; wire [79:0] gts_i_tx_parallel_data; wire [79:0] gts_o_rx_parallel_data; // jtag bridge wire write_bridge, read_bridge; wire [31:0] address_bridge; wire [31:0] writedata_bridge; wire [31:0] readdata_bridge; wire [3:0] byteenable_bridge; wire waitrequest_bridge; wire readdatavalid_bridge; // reset always @(posedge system_clk_100) begin if (system_reset) begin gts_i_tx_reset <= 1'b1; gts_i_rx_reset <= 1'b1; end else begin if((gts_o_tx_reset_ack==1'b1) && (gts_o_rx_reset_ack==1'b1)) begin gts_i_tx_reset <= 1'b0; gts_i_rx_reset <= 1'b0; end end end qsys_top soc_inst ( ... .intel_directphy_gts_0_i_rx_cdr_refclk_p_clk (REFCLK), .intel_directphy_gts_0_i_tx_pll_refclk_p_clk (REFCLK), .intel_directphy_gts_0_i_tx_reset_tx_reset (gts_i_tx_reset), .intel_directphy_gts_0_i_rx_reset_rx_reset (gts_i_rx_reset), .intel_directphy_gts_0_o_tx_reset_ack_tx_reset_ack (gts_o_tx_reset_ack), .intel_directphy_gts_0_o_rx_reset_ack_rx_reset_ack (gts_o_rx_reset_ack), .intel_directphy_gts_0_i_tx_parallel_data_i_tx_parallel_data (gts_i_tx_parallel_data), .intel_directphy_gts_0_o_rx_parallel_data_o_rx_parallel_data (gts_o_rx_parallel_data), .intel_directphy_gts_0_reconfig_write (write_bridge), .intel_directphy_gts_0_reconfig_read (read_bridge), .intel_directphy_gts_0_reconfig_address (address_bridge[17:0]), .intel_directphy_gts_0_reconfig_byteenable (byteenable_bridge), .intel_directphy_gts_0_reconfig_writedata (writedata_bridge), .intel_directphy_gts_0_reconfig_readdata (readdata_bridge), .intel_directphy_gts_0_reconfig_waitrequest (waitrequest_bridge), .intel_directphy_gts_0_reconfig_readdatavalid (readdatavalid_bridge), .gts_jtag_master_0_master_address (address_bridge), .gts_jtag_master_0_master_readdata (readdata_bridge), .gts_jtag_master_0_master_read (read_bridge), .gts_jtag_master_0_master_write (write_bridge), .gts_jtag_master_0_master_writedata (writedata_bridge), .gts_jtag_master_0_master_waitrequest (waitrequest_bridge), .gts_jtag_master_0_master_readdatavalid (readdatavalid_bridge), .gts_jtag_master_0_master_byteenable (byteenable_bridge), ... ); ... endmodule The boot output: TFTP from server **bleep**.**bleep**.xx.x; our IP address is **bleep**.**bleep**.xx.x Filename 'fpga/soc_system_base.rbf'. Load address: 0x90000000 Loading: ################################################################# ################################################################# ######### 2 MiB/s done Bytes transferred = 2031616 (1f0000 hex) ... FPGA reconfiguration failed!Command 'load' failed: Error -110 FPGA not ready. Bridge reset aborted! Did I overlook something? Any help would be greatly appreciated! Many thanks!
