Nikitha_Sree
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Loading the .POF in Arria 10 GX evaluation board
Hello everyone, I am trying to get a.pof file onto the Arria 10 GX evaluation board using the micro-USB connector. However, I am experiencing issues: Can't recognize the flash device that attached to device 2. The flash device is not supported by Quartus prime. Can't recognize silicon ID for device 2 Can't recognize the Flash device that attached to device 1. The Flash device is not supported by Quartus Prime software. I have some inquiries about: 1. Changing the board's switch settings. 2. Comprehensive guidelines for creating and loading.pof files, selecting parameters during the.pof file creation process, and loading.sof pages 1 or 0. 3. Additional details about the.jic file. Thanks, Nikitha.Re: Creating a Ibex component in platform designer on Arria 10 FPGA development board
Hi TingJiangT , Thanks for the response. Under the System --> Remove Dangling Connections is not been highlighted for selecting. Please find the screenshot for reference. Can you give me some information regarding the timer_sw_agent ,dm_agent in the Nios V Processor IP and there signals. Thanks NikithaRe: Creating a Ibex component in platform designer on Arria 10 FPGA development board
Hi TingJiangT , I developed a component (myriscv) with the AXI4 Manager bus for Instruction & Data Manager and internally assigned to clock, reset, and this is the master. When I try to connect to the JTAG UART IP and on chip memory IP as slaves, I got the following issues: Error: riscvcomp: Connection (post-transform) is missing an end point: riscvcomp_myriscv.dm_axi4_master->null Error: riscvcomp: Connection (post-transform) is missing an end point: riscvcomp_myriscv.im_axi4_master->null Error: riscvcomp: Connection (post-transform) is missing an end point: clock_in.out_clk->null Error: riscvcomp: Connection (post-transform) is missing an end point: clock_in.out_clk->null Error: riscvcomp: Connection (post-transform) is missing a start point: null->riscvcomp_jtag_uart.avalon_jtag_slave Error: riscvcomp: Connection (post-transform) is missing a start point: null->riscvcomp_intel_onchip_memorry.s1 Error: Internal Error: Cannot generate a system with dangling connections. Please look the screenshot attached for the reference. Please suggest the needful to be done. Thanks, NikithaCreating a Ibex component in platform designer on Arria 10 FPGA development board
Hello Everyone, I'am trying to create an Ibex component in the platform designer and trying to connect JTAG UART IP, On chip memory IP to that am facing the below connection errors : Error: riscvcomp: Connection (post-transform) is missing an end point: riscvcomp_myriscv.dm_axi4_master->null Error: riscvcomp: Connection (post-transform) is missing an end point: riscvcomp_myriscv.im_axi4_master->null Error: riscvcomp: Connection (post-transform) is missing an end point: clock_in.out_clk->null Error: riscvcomp: Connection (post-transform) is missing an end point: clock_in.out_clk->null Error: riscvcomp: Connection (post-transform) is missing a start point: null->riscvcomp_jtag_uart.avalon_jtag_slave Error: riscvcomp: Connection (post-transform) is missing a start point: null->riscvcomp_pio.s1 Error: riscvcomp: Connection (post-transform) is missing a start point: null->riscvcomp_intel_onchip_memorry.s1 Error: Internal Error: Cannot generate a system with dangling connections. Please find the attached screenshot for reference. Can anyone please provide how to resolve this issue thanks in advance .How to create a quartus project with .sv files and creating a custom IP on Arria10 GX FPGA Kit
Hello all, 1. I have .sv files and trying to create a Quartus project with that please let me know if there is any procedure for this . 2. Creating an Custom IP using .sv files which is equivalent to Nios V processor and integrate with other platform designer IP cores like jtag uart , on chip memory . please let me know if there is any procedure for this . Regards, NikithaRe: Arria 10 Gx FPGA Development Board
Hi Aik Eu, Regarding the license's syntax in .dat file , I have not discovered any problems according to the given link. I've attempted to launch Questa directly from the Start menu and replicate the Hello World in that: Expected output in transcript as per the PDF output in transcript i got Please provide your feedback on this. Regards, NikithaRe: Arria 10 Gx FPGA Development Board
Hi Aik Eu , thanks for the response. 1. When simulating the design using the vsim command with Questa for Intel FPGA simulator, I'm encountering errors. [niosv-shell] C:\intelFPGA_pro\24.1> vsim Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE) is set correctly and then run 'lmutil lmdiag' to diagnose the problem. Unable to checkout a license. Vsim is closing. ** Error: Invalid license environment. Application closing. This license cannot be checked out because: Invalid host. The hostid of this system does not match the hostid specified in the license file.Re: Arria 10 Gx FPGA Development Board
Hey Aikeu, Thanks for the inputs provided that helped a lot in starting the custom design. I couldn't use the Ready to test files (.sof files) on the evaluation board since the FPGA part number is different i.e Part number of the FPGA on evaluation board - 10AX115S2F45I1SG, I tried changing the FPGA part number directly in the Quartus and tried to compile but it didn't work like that. I have started designing the new code with the user guide provided, But I found an issue wrt the user guide 1. Select VID mode of operation in Configuration and Power Management Assignments - this is greyed out in my design can you suggest for this Please find the attached screen shots for reference.Arria 10 Gx FPGA Development Board
Hi , I'm presently working on the development kit for the Arria 10 Gx FPGA Development Board. We can execute the BTS test files included with the kit using Quartus Prime PRO 24.1 software, but when we try to import the custom design, we have the following questions. 1. Is soft processor support available for Arria 10GX? If yes, do provide us the reference design. 2. Is there a way to open the ports so that we may access the UART for debugging purposes? 3. Would you kindly assist us with the step-by-step process for developing platform designs using JTAG UART and 1G Ethernet IP?
