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Nikitha_Sree's avatar
Nikitha_Sree
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1 year ago

Arria 10 Gx FPGA Development Board

Hi ,

I'm presently working on the development kit for the Arria 10 Gx FPGA Development Board. We can execute the BTS test files included with the kit using Quartus Prime PRO 24.1 software, but when we try to import the custom design, we have the following questions.

1. Is soft processor support available for Arria 10GX? If yes, do provide us the reference design.
2. Is there a way to open the ports so that we may access the UART for debugging purposes?
3. Would you kindly assist us with the step-by-step process for developing platform designs using JTAG UART and 1G Ethernet IP?

Board Debug
Configuration
Programmable Logic Device

15 Replies

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi Nikitha_Sree,


    You can try the Nios V hello world example first:

    https://www.intel.com/content/www/us/en/design-example/788688/arria-10-fpga-hello-world-on-the-nios-v-g-processor-design-example.html

    This is a simple application to showcase a simple application(print hello world) running in the soft processor(NiosV).

    From this example, you can get to see the printf application showing the hello world logs through your Jtag connection.

    Before getting the application to run, you will compile the design in quartus then flash the design into the FPGA fabric through the same Jtag connection.


    For more details on Nios V tutorial related as reference:

    https://www.intel.com/content/www/us/en/docs/programmable/784468/current/an-985-processor-tutorial.html


    As for the migration to your custom project for reference:

    https://www.intel.com/content/www/us/en/docs/programmable/773196/current/overview.html


    Thanks.

    Regards,

    Aik Eu


    • Nikitha_Sree's avatar
      Nikitha_Sree
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hey Aikeu,

      Thanks for the inputs provided that helped a lot in starting the custom design.

      I couldn't use the Ready to test files (.sof files) on the evaluation board since the FPGA part number is different i.e Part number of the FPGA on evaluation board - 10AX115S2F45I1SG, I tried changing the FPGA part number directly in the Quartus and tried to compile but it didn't work like that.

      I have started designing the new code with the user guide provided, But I found an issue wrt the user guide

      1. Select VID mode of operation in Configuration and Power Management Assignments - this is greyed out in my design can you suggest for this

      Please find the attached screen shots for reference.

      • FvM's avatar
        FvM
        Icon for Super Contributor rankSuper Contributor
        1 year ago
        Hi,
        the .sof file is for Stratix 10, also power managment functions referenced in user guide are only available for Stratix 10 and can be ignored for Arria 10.
  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi Nikitha_Sree,


    You are not able to use the ready to test file from a Stratix10 project.

    The Stratix10 project is just the reference for how the design is done especially on the connections in Platform design. The pin assignment is something to be considered for migration.


    Thanks.

    Regards,

    Aik Eu


    • MattArnold's avatar
      MattArnold
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      1 year ago

      Hi @Nikitha_Sree,

      Just wanted to follow up on your question about the VID mode. FvM is right, that setting is for Stratix 10 and you can disregard it for Arria 10.

      Looks like Aik Eu already covered the .sof files being for Stratix too. The good news is you can still use them as a reference for your design connections, just be mindful of pin assignments when migrating to your Arria 10 board.

    • Nikitha_Sree's avatar
      Nikitha_Sree
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi Aik Eu ,

      thanks for the response.

      1. When simulating the design using the vsim command with Questa for Intel FPGA simulator, I'm encountering errors.

      [niosv-shell] C:\intelFPGA_pro\24.1> vsim
      Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE)
      is set correctly and then run 'lmutil lmdiag' to diagnose the problem.
      Unable to checkout a license. Vsim is closing.
      ** Error: Invalid license environment. Application closing.

      This license cannot be checked out because:
      Invalid host.
      The hostid of this system does not match the hostid specified in the license file.

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi Nikitha_Sree,


    Can check if you got any license requirement setup problem with the below for your quartus installation:

    https://www.intel.com/content/www/us/en/docs/programmable/683472/21-4/licensing-fpga-software.html

    Check the NIC ID on your setup:

    https://www.intel.com/content/www/us/en/docs/programmable/683472/21-4/identifying-host-s-nic-id.html


    The license is tied with your machine.

    Anyway to reconfirm, are you able to compile the design in quartus?



    Thanks.

    Regards,

    Aik Eu


    • Nikitha_Sree's avatar
      Nikitha_Sree
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi Aik Eu,

      Am able to compile the design in Quartus, and even able to check output - Hello world Prints on terminal

      I have followed the steps and installed the license files, even after that its still showing this error

      Regards,

      Nikitha

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi Nikitha_Sree,


    Any follow up from the issue? If no I will be closing the thread.


    Thanks.

    Regards,

    Aik Eu


    • Nikitha_Sree's avatar
      Nikitha_Sree
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi Aik Eu,

      Regarding the license's syntax in .dat file , I have not discovered any problems according to the given link.

      I've attempted to launch Questa directly from the Start menu and replicate the Hello World in that:

      Expected output in transcript as per the PDF

      output in transcript i got

      Please provide your feedback on this.

      Regards,

      Nikitha

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi Nikitha_Sree,


    Sorry for the late reply. Looks like the questa is running fine, may I know what is the problem again?


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi Nikitha_Sree,


    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Thanks.

    Regards,

    Aik Eu