Hey Aikeu,
Thanks for the inputs provided that helped a lot in starting the custom design.
I couldn't use the Ready to test files (.sof files) on the evaluation board since the FPGA part number is different i.e Part number of the FPGA on evaluation board - 10AX115S2F45I1SG, I tried changing the FPGA part number directly in the Quartus and tried to compile but it didn't work like that.
I have started designing the new code with the user guide provided, But I found an issue wrt the user guide
1. Select VID mode of operation in Configuration and Power Management Assignments - this is greyed out in my design can you suggest for this
Please find the attached screen shots for reference.