Danlar81
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Remote Update on Cyclone V
Hi, I'm trying to understand and identify all of the IP cores required to perform a Remote System Update using a Cyclone V (5CEFA9F23I7N) with a MT25QL01 flash chip. From what I have read it seems that I would require the following; Remote Update Intel FPGA IP with Avalon MM support Avalon MM Interface Generic Serial Flash Interface Intel FPGA IP Within the Remote Update user guide, it mentions you can bypass the Avalon MM interface, however this means I still need the ASMI Parallel II FPGA IP. The user manual for this core mentions it only supports EPCQ, EPCQ-L and EPCQ-A flash devices. Due to the flash I am using being third party it identifies the Generic serial flash mentioned above. Have I got this correct? Please advise. Regards, DanHDL import not supported for tri0
Hi, I am seeking some input for the following scenario. I have recently used Quartus to create a Remote Update module using Verilog. The plan was to import this into Simulink, because our firmware is developed in that environment. Using Simulink's importhdl function the relevant files began to parse until it reached the Tri-State declaration 'tri0' in the altera_remote_update_core.v file which is not supported. Is it possible to mask this at all? Or, would it be pointless to even try considering it forms the RU core? Lastly, I have read that enabling the RSU internal circuitry is done by selecting the Assignments tab and then clicking on the Device. I am using Quarus Prime Lite edition, which has most of the options under the Assignments tab 'Greyed' out. Does the ability to use the RSU internal circuity depend on having Quartus Prime 'Standard' edition if using Cyclone IV and/or V FPGA's? Regards, DanRe: Creating Bootloader within ROM using Cyclone V
Hi Frank, Thanks for the reply. I have looked into Remote Updates as suggested, and this looks to be the best method. However, I'm hoping you may be able to answer some further questions? It seems that a good approach would be to use the Remote Update IP Core which has the internal circuitry for communication with flash. However, the constraint is the UART interface. Assuming I created a UART Tx/Rx interface in VHDL, how do you go about interfacing that with the IP Core? Is that something that that is done in the Quartus via configuration settings? Would it be possible to create a design in Quartus which configured the Remote Update IP Core and flash which could be imported into Simulink using the HDL verifier toolbox? If that even worked I would not expect to see the contents of the remote Update IP core, I would only be after the block. From what I read, it didn't appear to be an issue not having control over the CONF_DONE, nCONFIG or nSTATUS pins when using the Remote Update IP Core. Is this correct, or have I got this wrong? I only ask, because the existing design currently uses these pins for programming via USB. The new RS-485 transceiver is connected to DIFFIO pins, therefore it would be ideal to interface via UART directly to the Remote Update IP Core. Regards, DanCreating Bootloader within ROM using Cyclone V
Hi, I'm looking to for some feedback/suggestions to the following. I have been tasked with creating a boot loader to be able to perform remote loading via serial interface. I initially did some research, and thought that the best way to perform this would be through 'Partial Reconfiguration', however I have since confirmed that the Cyclone V 5CEFA9F23I7N device I am working with does not support it. For some more context, the place I work for creates the firmware model within Simulink which is then synthesized via HDL coder and turned into a bit-stream via Quartus before loading onto the FPGA. Since discovering I am unable to use 'Partial Reconfiguration', I have thought about alternatives in concept, one of which is to potentially have the logic required to for the UART/RS-485 and SPI protocols in the firmware, along with the state machine to configure the external flash registers. The bit-stream would be received via RS-485, decoded then sent via SPI and written to flash. Assuming the bit-stream was complete, the FPGA would be reset and load the configuration from flash. I will admit, this sounds error prone and is the least preferred. The other alternative is to configure the FPGA internal ROM via .mif file, and have the ROM load the bit-stream into flash. This would mean the serial interface protocols would need to be stored within ROM, along with the code to configure the flash registers. I have read that the .mif can be written using HDL language such as VHDL, however I am wondering if it could be created via MATLAB script .m files? I have kept this at a pretty high level as I am just thinking about this conceptually, however I am looking for some advice given the situation presented. I'd be interested to know if anybody has had experience doing something like I have described before, and if so, what else should I consider? I'm a little uncertain about having the serial interfaces and state machine in ROM, as it's typically used to store configuration data. I'm not sure if it's even possible, or what the outcomes may be by trying to do this? Is there any resources that would be of further benefit which may aid the decision making, or introduce another alternative which have have not covered? Keen to hear all feedback. Regards, DanRe: VHDL AND Logic working as OR logic
Hi, I have it all working now which is good news. I am familiar with boolean, however I was trying a lot of new concepts for the first time. I was also performing the logic in Simulink and downloading to the FPGA. I think I was a little blinded by trying to ensure the many settings that were necessary between Quartus and Simulink were ok, I just didn't pay enough attention to the hardware side of things. As soon as I looked at the schematic again after FvM's comments it was very obvious what what the problem was. Thank you for your response.VHDL AND Logic working as OR logic
Hello, I am fairly new to VHDL programming. I purchased a Udemy online course to begin learning along with a cheap Chinese development board which is used in the course, see link below. The dev board uses a Cyclone IV EP4CE6E22 FPGA. I have installed Quartus Prime Lite 20.1 to write the VHDL code and program the device. However, I am running into problems trying to implement simple AND gate logic. I have mapped two external switch inputs and one LED output, but if I press either one of the external switches the LED illuminates, so therefore the logic is behaving as an OR. I have tried all the switch inputs and all LED outputs individually with no logic and the correct LED illuminates when the assigned switch is depressed. So I am getting very confused as to why I would be seeing OR type logic when I have implemented an AND. I have attached a screenshot of my VHDL code, so it can be confirmed that I have implemented the AND operation correctly. Is there any further settings that I would need to be aware of in Quartus, that may explain the behavior I am experiencing? I'm still no ruling out, that this could be related to the development board, however I would prefer some further feedback prior to trying to send it back to receive a refund. Please advise. <FPGA Dev Board>
