RHobb
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Re: Example Project for Hardware Verification Uses Outdated drivers for PCI Express
I would like community feedback on this, so you can close this out and transition this so others may comment on this. I was unable to simply update the kernel device drivers, because the API device drivers are tied to a specific kernel build, in this instance, CentOS 7.3 is the only OS that has the 3.10.514 kernel that was used to build the example project.172Views0likes0CommentsExample Project for Hardware Verification Uses Outdated drivers for PCI Express
So I'm trying to download the design example as explained in the L-tile and H-tile Avalon® Memorymapped Intel® FPGA IP for PCI Express* User Guide, and even the MM+ variant, or even the Avalon ST design example but I am running into known issues. As noted in the Memorymapped Intel® FPGA IP for PCI Express* User Guide, on p. 18 it says "Operating System: CentOS 7.0, 64-bit with 3.10.514 kernel compiled for x86_64 architecture" Please note, this CentOS was released almost 10 years ago in 2016. I can compile the code in Quartus in CentOS 10 (coughlin) which is the streaming version that uses a completely different kernel 6.12, so it will not work or compile with errors using the instructions on p. 23. I also have a dual boot setup with Windows 11 being my main OS, but even then the design example relies on a Linux OS. I have a modern PC (Asus motherboard with AMD Ryzen 9 7950x3D) that is unable to run CentOS 7.3 (1611) with the 3.10.514 kernel, nor can I run a VM to run this. The hardware is simply way too new for this architecture. Can someone please assist at a solution? I have seen earlier FPGA boards that provides complete driver solutions and designs for the Aria based boards and supplies software and drivers for Windows users, as noted in AN708, but none of the newer FPGA, like Stratix 10 which I'm working on.467Views0likes4CommentsFailed to load design on Stratix 10 FPGA with PCI Express Design Example
I'm validating the actual working design example from the User Guide L-Tile/H-Tile Memory Mapped+ for PCI Express, I have no issue compiling the design example using the included pcie.ip variant for my board, it's a Terasic Apollo S10 SoM with the 1SX280HU2F50E1VG. When I go to program the board, it fails at 80% with the following error messages: Error(18950): Device has stopped receiving configuration data Error(18948): Error message received from device: Device is in configuration state. Error(209012): Operation failed To confirm it's not a board issue, I use some of the example projects included with my board in the demonstration folder, and it works fine in Linux (CentOS 10 - Coughlin). I've ported my designs from Windows to Linux, so Terasic does offer the option to use there SystemBuilder app on Windows to generate all the .qsf files and .sdc files including main project, and I just port it over to my Linux environment, using these standard assignments. Intel has reported there is a bug in the environment, Bug ID: 1508562679 which states this problem was fixed in version 20.4. I'm using version 25.1.0. What else could cause a configuration issue to stop at 80%? I believe I did read a refclock would need to be generated into the design, but I believe the Linux driver does all this for testing.246Views0likes2CommentsRe: Unable to install kernel driver for testing PCI Express
I want to close this thread as an acceptable answer, but I have encountered another more serious problem. I will also go back and fix the updated kernal API drivers manually to fix the issue. The issue I'm having is actually programming my board, after I successfully generated the design example, compiled, set the .qsf file settings to the recommended pin assignments in the design example folder. It keeps stopping at 80% and outputs this error message: Error(18950): Device has stopped receiving configuration data Error(209012): Operation failed Error(18948): Error message received from device: Device is in configuration state. There is an internal Bug ID: 1508562679 that addresses this known issues with the Stratix10 fpga which states : Resolution This problem is fixed starting in Intel® Quartus® Prime Pro Edition Software version 20.4. I have a running reference clock assigned, which is provided on the Terasic Apollo S10 SoM. Can you assist in a solution?311Views0likes0CommentsUnable to install kernel driver for testing PCI Express
I'm referencing the L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express User Guide (2024.09.13). On page 19 and after compiling the design example, it wants the user to install the Linux kernel driver which tests the PCI link for reads/writes. After I change the permission on the install, load and unload files, I then install the driver using sudo ./install it outputs a lot of errors. make -C /lib/modules/6.12.0-120.el10.x86_64/build M=/home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux clean make[1]: Entering directory '/usr/src/kernels/6.12.0-120.el10.x86_64' make[1]: Leaving directory '/usr/src/kernels/6.12.0-120.el10.x86_64' make -C /lib/modules/6.12.0-120.el10.x86_64/build M=/home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux modules make[1]: Entering directory '/usr/src/kernels/6.12.0-120.el10.x86_64' CC [M] /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_chr.o /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_chr.c: In function ‘chr_mmap’: /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_chr.c:313:19: error: assignment of read-only member ‘vm_flags’ 313 | vma->vm_flags |= VM_PFNMAP | VM_DONTCOPY | VM_DONTEXPAND; | ^~ In file included from ./include/linux/printk.h:6, from ./include/linux/kernel.h:31, from ./include/linux/cpumask.h:11, from ./include/linux/smp.h:13, from ./include/linux/lockdep.h:14, from ./include/linux/mutex.h:17, from ./include/linux/kernfs.h:11, from ./include/linux/sysfs.h:16, from ./include/linux/kobject.h:20, from ./include/linux/cdev.h:5, from /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_setup.h:47, from /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_chr.h:47, from /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_chr.c:45: /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_chr.c: In function ‘intel_fpga_pcie_chr_init’: ./include/linux/init.h:180:22: error: passing argument 1 of ‘class_create’ from incompatible pointer type [-Wincompatible-pointer-types] 180 | #define THIS_MODULE (&__this_module) | ~^~~~~~~~~~~~~~~ | | | struct module * /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_chr.c:355:40: note: in expansion of macro ‘THIS_MODULE’ 355 | global_bk.chr_class = class_create(THIS_MODULE, | ^~~~~~~~~~~ In file included from ./include/linux/device.h:30, from ./include/linux/cdev.h:8: ./include/linux/device/class.h:226:54: note: expected ‘const char *’ but argument is of type ‘struct module *’ 226 | struct class * __must_check class_create(const char *name); | ~~~~~~~~~~~~^~~~ /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_chr.c:355:27: error: too many arguments to function ‘class_create’ 355 | global_bk.chr_class = class_create(THIS_MODULE, | ^~~~~~~~~~~~ ./include/linux/device/class.h:226:29: note: declared here 226 | struct class * __must_check class_create(const char *name); | ^~~~~~~~~~~~ /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_chr.c: In function ‘chr_access’: /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_chr.c:536:50: error: macro "access_ok" passed 3 arguments, but takes just 2 536 | if(! access_ok(VERIFY_WRITE, buf, sizeof(buf))) { | ^ In file included from ./arch/x86/include/asm/uaccess.h:25, from ./include/linux/uaccess.h:12, from ./include/linux/sched/task.h:13, from ./include/linux/sched/signal.h:9, from ./include/linux/rcuwait.h:6, from ./include/linux/percpu-rwsem.h:7, from ./include/linux/fs.h:33, from ./include/linux/compat.h:17, from ./arch/x86/include/asm/ia32.h:7, from ./arch/x86/include/asm/elf.h:10, from ./include/linux/elf.h:6, from ./include/linux/module.h:19, from ./include/linux/device/driver.h:21, from ./include/linux/device.h:32: ./include/asm-generic/access_ok.h:45:9: note: macro "access_ok" defined here 45 | #define access_ok(addr, size) likely(__access_ok(addr, size)) | ^~~~~~~~~ /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_chr.c:536:10: error: ‘access_ok’ undeclared (first use in this function) 536 | if(! access_ok(VERIFY_WRITE, buf, sizeof(buf))) { | ^~~~~~~~~ /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_chr.c:536:10: note: each undeclared identifier is reported only once for each function it appears in make[3]: *** [scripts/Makefile.build:229: /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux/intel_fpga_pcie_chr.o] Error 1 make[2]: *** [/usr/src/kernels/6.12.0-120.el10.x86_64/Makefile:1994: /home/rhobbs/Documents/avmm_bridge_512_0_example_design/software/kernel/linux] Error 2 make[1]: *** [Makefile:242: __sub-make] Error 2 make[1]: Leaving directory '/usr/src/kernels/6.12.0-120.el10.x86_64' make: *** [Makefile:17: all] Error 2 insmod: ERROR: could not load module ./intel_fpga_pcie_drv.ko: No such file or directory Could someone please tell me what corrections are needed to install the driver? After I did that, I then proceeded to step 4 which says verify the driver installation, and it lists nothing, so it did not work. This is supposed to be an out of the box solution, you just perform the steps to install the driver. I need someone to please verify it works on there machine as well. For reference, this was done on CentOS 10 [Coughlin] using Quartus Prime Pro Edition 25.1 (latest) ThanksSolved519Views0likes3CommentsRe: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa
Solved! But there are some points I want addressed. So everything worked in CentOS (10.0). I compiled the design for the PCI Express 3.0 x8 using the standard MM option, the generated design example did compile but it ended up failing because there was no stimulus, so it ran until 4 seconds and quit. (took 8 hours to complete) I then ran the other option, the PCI Express 3.0 x 16 (MM+) which automatically downtrains to x8, in the IP Generation dialogue box it does give you the option to have Intel BFM to apply, so I did that, compiled in QuestaSim and it ran to completion, everything worked. So why doesn't the User Manual explain if you run the standard x8 option that you have to supply your own testbench stimulus? And why doesn't the IP editor allow you to apply the Intel BFM for just the x8 option? In regards to switching to CentOS and disregarding my Windows problem, I feel like Quartus should be able to recognize spaces between names in the user path, and all this confusion could have been resolved and I could have proceeded with the Windows environment. The space between "Valued Customer" in my user downloaded configuration path that Quartus used DID created problems. I made sure to avoid any spaces during my CentOS installation and used short paths. Thanks for all the help and I hope this helps others out.403Views0likes0CommentsRe: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa
Sorry for the delay. The problem was with my Windows install, it has a space in a directory that has all my config data for all my programs. I ported the design over to CentOS 10, the latest update. It compiled in QuestaSim, took over 8 hours to simulate then failed. I used the design you sent me. I could not see any simulation waveforms. Will try again. If you don't mind, can you please append the WLF data? Once your simulation succeeds, it should post a message and ending the simulation run. I'm interested in the waveform data which you can save from the File menu. I can at least load this data in the advent there is another failure. Thank you438Views0likes0CommentsRe: Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa
I updated my simulator from the ModelSim Starter Ed and Questa Starter to Siemens Questa, Questa Intel FPGA Ed-64 2024.3 and ran all the previous commands as outlined in the User Guide and I am still getting the "failed to load design" after generating 3000+ errors as previously I got. This leads me to believe there is something I'm not checking in the IP variant checkboxes. I contend, everything was followed according to the User Guide. Can you please upload your complete folder including the IP variant for my device you generated and upload it to FileTransfer.io or SendGB, which is a free hosting site for files up to 5GB ? Once I receive this, and find out where my errors orginiated from and after sucessful simulation, I'll mark this as Solved and explain what I did wrong.7.6KViews0likes0Comments