Forum Discussion

RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate. This is for Quartus Prime Design Suite 23.4. I followed the p...
Pcie
  • RongY_altera's avatar
    RongY_altera
    11 months ago

    Thanks for the sharing of your conclusion and findings.


    You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.


    Regards,

    Rong


RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
11 months ago

Sorry for the delay.

The problem was with my Windows install, it has a space in a directory that has all my config data for all my programs. I ported the design over to CentOS 10, the latest update. It compiled in QuestaSim, took over 8 hours to simulate then failed. I used the design you sent me. I could not see any simulation waveforms.

Will try again.

If you don't mind, can you please append the WLF data? Once your simulation succeeds, it should post a message and ending the simulation run. I'm interested in the waveform data which you can save from the File menu. I can at least load this data in the advent there is another failure.

Thank you