Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

Solved!

But there are some points I want addressed.

So everything worked in CentOS (10.0). I compiled the design for the PCI Express 3.0 x8 using the standard MM option, the generated design example did compile but it ended up failing because there was no stimulus, so it ran until 4 seconds and quit. (took 8 hours to complete)

I then ran the other option, the PCI Express 3.0 x 16 (MM+) which automatically downtrains to x8, in the IP Generation dialogue box it does give you the option to have Intel BFM to apply, so I did that, compiled in QuestaSim and it ran to completion, everything worked.

So why doesn't the User Manual explain if you run the standard x8 option that you have to supply your own testbench stimulus? And why doesn't the IP editor allow you to apply the Intel BFM for just the x8 option?

In regards to switching to CentOS and disregarding my Windows problem, I feel like Quartus should be able to recognize spaces between names in the user path, and all this confusion could have been resolved and I could have proceeded with the Windows environment. The space between "Valued Customer" in my user downloaded configuration path that Quartus used DID created problems. I made sure to avoid any spaces during my CentOS installation and used short paths.

Thanks for all the help and I hope this helps others out.