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RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate. This is for Quartus Prime Design Suite 23.4. I followed the p...
Pcie
  • RongY_altera's avatar
    RongY_altera
    11 months ago

    Thanks for the sharing of your conclusion and findings.


    You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.


    Regards,

    Rong


RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
11 months ago

I updated my simulator from the ModelSim Starter Ed and Questa Starter to Siemens Questa, Questa Intel FPGA Ed-64 2024.3 and ran all the previous commands as outlined in the User Guide and I am still getting the "failed to load design" after generating 3000+ errors as previously I got. This leads me to believe there is something I'm not checking in the IP variant checkboxes. I contend, everything was followed according to the User Guide.

Can you please upload your complete folder including the IP variant for my device you generated and upload it to FileTransfer.io or SendGB, which is a free hosting site for files up to 5GB ? Once I receive this, and find out where my errors orginiated from and after sucessful simulation, I'll mark this as Solved and explain what I did wrong.