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RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

Failed to load design on Stratix 10 FPGA with PCI Express Design Example

I'm validating the actual working design example from the User Guide L-Tile/H-Tile Memory Mapped+ for PCI Express, I have no issue compiling the design example using the included pcie.ip variant for my board, it's a Terasic Apollo S10 SoM with the 1SX280HU2F50E1VG.

When I go to program the board, it fails at 80% with the following error messages:

Error(18950): Device has stopped receiving configuration data
Error(18948): Error message received from device: Device is in configuration state.
Error(209012): Operation failed

To confirm it's not a board issue, I use some of the example projects included with my board in the demonstration folder, and it works fine in Linux (CentOS 10 - Coughlin). I've ported my designs from Windows to Linux, so Terasic does offer the option to use there SystemBuilder app on Windows to generate all the .qsf files and .sdc files including main project, and I just port it over to my Linux environment, using these standard assignments.

Intel has reported there is a bug in the environment, Bug ID: 1508562679 which states this problem was fixed in version 20.4. I'm using version 25.1.0. What else could cause a configuration issue to stop at 80%? I believe I did read a refclock would need to be generated into the design, but I believe the Linux driver does all this for testing.

2 Replies

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hello,


    Error (18950) : Device stopped receiving configuration data

    Error (18948) : Device is in configuration state

    Error (209012) : Operation failed


    Can you check below items:

    1-PCIe refclk is alive?

    2- Pin assignments correct? esp. the refclk and PERST#.

    3- Power rails -esp. VCCR_GXB and VCCH_GXB rails.

    4-PMBus configuration and smartVID settings- can your design compile successfully and able to generate the .sof file?

    If yes, then please re-check the smartVID configuration settings.

    5- Bug ID 1508562679 was resolved in Quartus Pro 20.4, and you are using 25.1.0 should be no issue, however, please check your IP are they upgraded as well?


    6-If you run simple design can the FPGA configured successfully? This is to rule out the board issue.


    regards,

    Farabi