Failed to load design on Stratix 10 FPGA with PCI Express Design Example

Hello,

Error (18950) : Device stopped receiving configuration data

Error (18948) : Device is in configuration state

Error (209012) : Operation failed

Can you check below items:

1-PCIe refclk is alive?

2- Pin assignments correct? esp. the refclk and PERST#.

3- Power rails -esp. VCCR_GXB and VCCH_GXB rails.

4-PMBus configuration and smartVID settings- can your design compile successfully and able to generate the .sof file?

If yes, then please re-check the smartVID configuration settings.

5- Bug ID 1508562679 was resolved in Quartus Pro 20.4, and you are using 25.1.0 should be no issue, however, please check your IP are they upgraded as well?

6-If you run simple design can the FPGA configured successfully? This is to rule out the board issue.

regards,

Farabi