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Re: writing a word to cfm1 using on chip flash ip on max10
hii good morning , i found out something that got under my radar sort of speak , i built a qsys system with pll that feeds the on chip flash ip and the dual configuration ip , and my logic for reading and writing worked directly from the on board osc , so infact even if the clk is 50mhz the same . the outputs from the pll and 50mhz from osc ,they are separate time domains i removed the pll from the design and worked with the on board osc clk only for my logic and for the altera ip and it worked i dont have any failures any more , i still need to test the design with reduced delay between the sent rpd words . i will check on that14Views0likes2CommentsRe: writing a word to cfm1 using on chip flash ip on max10
hii I receive the RPD data through a serial UART interface, and I can control the time delay between each transmitted word (4 bytes). What I noticed is that when the delay is about 2.5 ms between each word, I can write the RPD successfully without errors. However, when I try to decrease the delay between the words down to 1.5 ms, I start to get these errors. My logic performs the write operation and verifies the write success within the delay period between the words received through the UART. I should also state that I used a 50 MHz clock for my design. I tried lowering the clock frequency to see if it would help, so currently my system is running at 50 MHz. I also observed the waitrequest signal by routing it to a header pin on my board and probing it with my own logic analyzer. I noticed that the pulse width of the waitrequest signal ranges from a few hundred microseconds up to more than 1000 microseconds and even more. However, the datasheet states that the maximum pulse width should be around 350 microseconds, which is not the timing I am seeing on the logic analyzer. Is the pulse width of the waitrequest signal that I observed on the logic analyzer normal? I checked my design and found that there is indeed a timing issue that I still need to fix. However, I encounter these errors only when I decrease the delay between the words sent through the serial UART in order to reduce the time needed to update the new image in the FPGA CFM.3Views0likes0CommentsRe: writing a word to cfm1 using on chip flash ip on max10
hii yes i write a 32 bit of data on avmm_data_writedata on the avalon bus , and i set the burstcount to 1 i hold the avmm_write<='1' as long as waitrequest=1 , and when i receive waitrequest=0 i disable the avmm_write , update the next address and move to the next data to write As noted earlier, write operations generally succeed when I verify the success flags in the CSR status register. However, I occasionally encounter a write failure when writing a 32-bit word, even though previous writes completed successfully.39Views0likes2Commentswriting a word to cfm1 using on chip flash ip on max10
hii i have the neek board development kit , and i am writing my own logic to perform a writing of an image to cfm1 flash sector for remote update i am transferring the image through uart from rpd file just like in nios rsu example lab . i configured the on chip flash ip in this parameters data interface :parallel read burst mode :incrementing read burst count:8 configuration mode :dual compressed images i set the burstcount to 1 I managed to erase the CFM1 sector, and I read the status register to confirm that the erase of sectors 3 and 4 was successful. Sector 3 + 4 corresponds to CFM1. Before performing the write operation, I verify that the on-chip flash is in the idle state by reading the CSR status register. I place the word on the data_writedata signal of the Avalon bus with the correct address, assert the data_write signal, and then wait until waitrequest goes low before proceeding to the next word. I confirm that the write was successful by reading the ‘write successful’ bit in the CSR status register. but sometimes in the middle of the file transfer , i get a write failure and i am not sure why , my clock on board is 50 mhz and i am using pll to generate 75mhz. so i i am feeding the 75mhz clock to the on chip flash ip and my own writing fsm logic Using SignalTap, I can see that the word before the one where the write failed was written successfully. I send each word over the UART interface with a delay of 2.5 ms, which I believe is sufficient for the write to complete. I also check the waitrequest signal before proceeding to the next word and verify that the on-chip flash is in the idle state.” I would be thankful to know why I am getting a write failure and what I should check to resolve this issue? thanks194Views0likes15CommentsRe: USING SIGNAL TAP TO MONOTOR AVALON_BUS WITH NIOS DESIGN
hii thanks for your reply and help , i did something that i expected it will work but i didn't. i added signal tap to the design and compiled the design converted it into pof file type , and programmed it to cfm0 and didn't work , but when i programmed my max10 with a sof file i managed to monitor the signals of the avalon bus on the on chip flash ip , but all of the above are helpfull tips , hope it will help me in future designs.41Views1like2CommentsUSING SIGNAL TAP TO MONOTOR AVALON_BUS WITH NIOS DESIGN
hii i need to use signal tap to see what's happening on avalon bus , i have a qsys system that is working fine , its the remote update example , and when i add a signal tap file and add for example the avalon bus signals the connects to the on chip flash ip , and i try to write the cfm0 the signal tap does not work . i put the trigger on a rising edge of a avalon_write and nothing seems to happen , i be glad for help :)80Views0likes4Comments