Chris039
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Re: How to fix setup violation for signal tap?
Hi Richard, The timing violation is actually a hold but not setup. I apologies for the mistake about the setup violation -Try to add pipeline factor (maximum 5) It is a clock input signal and not the real data signal. I am not sure can add the pipeline to clock signal or not Could you share screenshot of the failed timing path's "Data Arrival Path" in the "Data Path" and the "Statistic" Report in the Timing Analyzer? What is the number of logic levels?Re: How to fix setup violation for signal tap?
Hi Richard, I cannot share the design for confidential information. I tried to create a simple design but the timing violation does not occur in the simple design. The timing violation occur from the input clock port to the signal tap data signal, what we can try to fix this?
