Chris039
Occasional Contributor
Occasional ContributorHow to fix setup violation for signal tap?
Hi, How to fix the setup violation for the signals below? clk is the clock signal that I set in the signal tap. Thanks
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Chris039Occasional Contributor
Occasional ContributorHi Richard,
I cannot share the design for confidential information. I tried to create a simple design but the timing violation does not occur in the simple design. The timing violation occur from the input clock port to the signal tap data signal, what we can try to fix this?
