snehal_p
ContributorJoined 4 years ago
User Profile
Contributor
User Widgets
Contributions
Re: NIOS 2 for QSPI boot
Hello BB, We verified the QSPI controller instantiation in platform designer and correct based address (0x1800000) matches the memory map in linker scripts. We tried to program qspi using programmer but it fails. Can you please share steps to verify the read/write by flashing the Nios ii firmware into the EPCQ. Thanks, snehal_p838Views0likes0CommentsNIOS 2 for QSPI boot
Hello, We are trying to boot NIOS 2 processor from QSPI(EPCQ64ASI16N) on customized cyclone V board(HPS is not usable). As of now we are trying to perform a memory test on Nios2 processor, facing issues while testing qspi memory. Below is the memory test log, <----> Nios II Memory Test. <----> This software example tests the memory in your system to assure it is working properly. This test is destructive to the contents of the memory it tests. Assure the memory being tested does not contain the executable or data sections of this code or the exception address of the system. Press enter to continue or 'q' to quit. Base address to start memory test: (i.e. 0x800000) >0x800020 0x800020 End Address: >0xFFFFFE 0xFFFFFE Testing RAM from 0x800000 to 0xFFFFFE -Data bus test failed at bit 0x1 Press enter to continue or 'q' to quit. Base address to start memory test: (i.e. 0x800000) >0x1040020 0x1040020 End Address: >0x1060F73 0x1060F73 Testing RAM from 0x1040020 to 0x1060F73 -Data bus test passed -Address bus test passed -Byte and half-word access test passed -Testing each bit in memory device. Also find the linker script below, #ifndef __LINKER_H_ #define __LINKER_H_ /* * BSP controls alt_load() behavior in crt0. */ #define ALT_LOAD_EXPLICITLY_CONTROLLED /* * Base address and span (size in bytes) of each linker region */ #define EPCQ_CONTROLLER2_0_AVL_MEM_REGION_BASE 0x1800000 #define EPCQ_CONTROLLER2_0_AVL_MEM_REGION_SPAN 8388608 #define ONCHIP_MEMORY2_0_REGION_BASE 0x2040020 #define ONCHIP_MEMORY2_0_REGION_SPAN 135092 #define RESET_REGION_BASE 0x2040000 #define RESET_REGION_SPAN 32 /* * Devices associated with code sections */ #define ALT_EXCEPTIONS_DEVICE ONCHIP_MEMORY2_0 #define ALT_RESET_DEVICE ONCHIP_MEMORY2_0 #define ALT_RODATA_DEVICE ONCHIP_MEMORY2_0 #define ALT_RWDATA_DEVICE ONCHIP_MEMORY2_0 #define ALT_TEXT_DEVICE ONCHIP_MEMORY2_0 /* * Initialization code at the reset address is allowed (e.g. no external bootloader). */ #define ALT_ALLOW_CODE_AT_RESET /* * The alt_load() facility is called from crt0 to copy sections into RAM. */ #define ALT_LOAD_COPY_RWDATA #endif /* __LINKER_H_ */ Thanks, snehal_p1.5KViews0likes6CommentsUsing EMAC hps peripheral in FPGA mode
Hello, I'm evaluating Cyclone V customized board. Using EMAC hps peripheral in FPGA mii mode, a MII to RMII converter to drive RMII Phy at 100Mbps. Phy is being detected but could not establish connectivity. Need help to understand the issue. Thanks, snehal_p799Views0likes5CommentsRe: Building uboot for cyclone V SoC
Hello, We are currently working with Quartus Prime Standard Edition v22.1 and have noticed that it no longer includes the embedded_command_shell file, which was previously available in earlier versions as part of the SoC-EDS. This shell was essential for launching tools like bsp-editor and mkpimage used to generate the preloader for the Cyclone V SoC. While following the "Building Bootloader for Cyclone V and Arria 10" guide, I am able to successfully boot the HPS and access all its peripherals. However, the FPGA does not get configured - only the HPS boots correctly, and the FPGA remains unconfigured, even when using an updated .rbf file. Interestingly, this issue does not occur when using Quartus v18.1 - in that version, both the HPS and FPGA configure as expected. This suggests that something may have changed or is missing in the newer version's flow. Could you please advise if there is a new procedure or an additional step required in v22.1 to ensure the FPGA bitstream is loaded properly during boot? Looking forward to your guidance on resolving this issue. Thanks, snehal_p933Views0likes0Commentsboot file generation using quartus 22.1 standard version
Hello, We want to build boot image for customized cyclone V SoC board. We are following the below document, using Quartus Prime 22.1 Standard Edition on Ubuntu 20.04 system, https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Appendix_45_Building_Linux_Binaries It is our observation that the FPGA is not being programmed by the rbf file in the fat partition of the sd card. Can you please share your suggestions/pointers on the above. Thanks, snehal_p746Views0likes4CommentsRe: Building uboot for cyclone V SoC
Hello, 1) Are you using 2 different UART baudrate for the linux and uboot? -- during built can we select baudrate, PFA uboot and device tree 2) Following the steps https://www.rocketboards.org/foswiki/Documentation/HOWTOCreateADevicetreeForCycloneVSoC, we could generate a dts file for customized board but facing issue while generating a dtb file. Below is the error message DTC arch/arm/boot/dts/my_cv_fpga_overlay.dtb Error: arch/arm/boot/dts/my_cv_fpga_overlay.dts:50.10-11 syntax error FATAL ERROR: Unable to parse input tree make[1]: *** [scripts/Makefile.lib:351: arch/arm/boot/dts/my_cv_fpga_overlay.dtb] Error 1 make: *** [Makefile:1403: my_cv_fpga_overlay.dtb] Error 2 PFA header and dts file generated, as per our observation dts is not being updated wrt to header file generated.. Can you please share the pointers. Thanks and regards, snehal_p1.1KViews0likes0CommentsRe: Building uboot for cyclone V SoC
Hello, Can you help with command to generate dts with sopcinfo and board xml files as input. The below command works in SOC EDS, which is discontinued in Quartus 22.1 sopc2dts --input soc_system.sopcinfo\ --output soc_system.dts\ --type dts\ --board soc_system_board_info.xml\ --board hps_common_board_info.xml\ --bridge-removal all\ --clocks Thanks, snehal_p3.2KViews0likes0CommentsRe: Building uboot for cyclone V SoC
Hello, 1) PFA debug log images, Image_1 is when baud in 115200 uboot boot log is visible but as soon as it goes to kernel config then it shows garbage data, if baud changed to 230400 then uboot boot log is not visible garbage data but kernel boot log can be seen after that all system runs on 230400 baud even able to run the application. 2) PFA debug log, we have enabled emac 0 hps peripheral in fpga mode. But ethernet is not being detected. Is it because we are using dtb file generated by the steps mentioned in the below document. Do we need to generate dtb by some other steps, if yes please share the steps. https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Appendix_45_Building_Linux_Binaries Thanks, snehal_p3.3KViews0likes0Comments