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snehal_p's avatar
snehal_p
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10 months ago
Solved

Building uboot for cyclone V SoC

Hello, We want to build boot image for customized cyclone V SoC board. We are following the below document, using Quartus Prime 22.1 Standard Edition on Ubuntu 20.04 system, https://www.rocketb...
Fpga Devkit
  • tehjingy_Altera's avatar
    tehjingy_Altera
    7 months ago

    Hi Snehal


    Just to update the forum case.

    The missing steps from the RBO page are the steps below:


    1.Step to convert the sof to rbf. You could use the command below to convert the sof.

    quartus_cpf -c -o bitstream_compression=on soc_system.sof soc_system.rbf


    2.Missing u-boot.scr could be gotten from the gsrd page.

    https://releases.rocketboards.org/2025.03/gsrd/c5_gsrd/u-boot.scr


    3.Place both rbf and the u-boot.scr in the sdcard partition 1 (sdfs)


    Regards

    Jingyang, Teh


tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
7 months ago

Hi


Do you have any more follow up question on this issue?


Regards

Jingyang,Teh


snehal_p's avatar
snehal_p
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7 months ago

Hello,

We are currently working with Quartus Prime Standard Edition v22.1 and have noticed that it no longer includes the embedded_command_shell file, which was previously available in earlier versions as part of the SoC-EDS. This shell was essential for launching tools like bsp-editor and mkpimage used to generate the preloader for the Cyclone V SoC.
While following the "Building Bootloader for Cyclone V and Arria 10" guide, I am able to successfully boot the HPS and access all its peripherals. However, the FPGA does not get configured - only the HPS boots correctly, and the FPGA remains unconfigured, even when using an updated .rbf file.
Interestingly, this issue does not occur when using Quartus v18.1 - in that version, both the HPS and FPGA configure as expected. This suggests that something may have changed or is missing in the newer version's flow.
Could you please advise if there is a new procedure or an additional step required in v22.1 to ensure the FPGA bitstream is loaded properly during boot?
Looking forward to your guidance on resolving this issue.
Thanks,
snehal_p