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Hamathon
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Cyclone V eMMC bare metal example
Hi, I am able to run the SD/MMC example from the FPGA Bare-metal Developer Center with an SD card. Now, I'd like to do the same with an eMMC. My questions are: 1. Are eMMC supported by the HWLIB? The SD/MMC driver specifically says MMC are not supported. Is it possible using the NAND HWLIB? 2. I just want to check if there is an example for eMMC cards? I am using a Cyclone V SX SOM with a built-in eMMC. Any advice to help get a working example up and running would be appreciated. Thanks.615Views0likes2CommentsCyclone V SX Bare Metal Example - EMMC
Hi, I am able to run the SD/MMC example from the FPGA Bare-metal Developer Center. Now, I'd like to do the same with an eMMC. My questions are: 1. Are eMMC supported by the HWLIB? (is it the NAND HWLIB?) 2. I just want to check if there is an example for eMMC cards? I am using a Cyclone V SX SOM with a built-in eMMC. Any advice to help get a working example up and running would be appreciated. Thanks.492Views0likes1CommentClocking Cyclone V Native PHY IP using Altera fractional PLL IP (LVDS Mode)
I'm trying to use the altera pll IP to clock (100mhz, lvds mode) the tx and rx cdr ref clock of the native phy IP. However, I'm receiving error messages during fitting saying that Quartus cannot find an available fpll location. This is for a board using Cyclone V SX C2 model without an external crystal oscillator driving the transceiver bank. I tried using the ALTCTRL IP to set the PLL clock as a global clock based on another message board post but it did not work. Prior to this, I used this exact same Native Phy verilog code (xcvr, reconfig, reset) for an Intel C5 SX Dev Kit. I was able to clock the IP using the 100mhz hardware oscillator on that board and have the IP working correctly. Is there something I'm missing, configuration or otherwise, when I switch from using a hardware crystal oscillator to using the alterall pll? I saw from previous posts that there used to be a Cyclone V fpll example for native phy IP, but I can't seem to find it anymore as the wiki links are broken. Looking for advice and/or access to the example fpll native PHY IP. Thanks.1.1KViews0likes4CommentsWord Alignment - Custom Phy- Native Phy
Hi, I am trying to send data between 2 dev boards (1 Intel Cyclone 5 Soc Kit and 1 Terasic Cyclone 5 GX starter kit) together using fiber optic SFP. Both dev boards have the terasic SFP daughter board attached to them via HSMC. I am running into an issue where the sync_sm mode for the RX word alignment mode parameter does not seem to function properly. -I am using 8b/10b -I am using 1 channel (1 fiber optic cable) -Clock is being sent and is aligning properly Whenever I send data using the custom phy native phy IP, it seems that the Rx side is locking onto the clock at random without performing any bit slip. Sometimes it syncs correctly sometimes it doesn't, which leads me to believe that the sync_sm mode is not cycling through the bits correctly. According to a previous reply by an Intel employee: "As for state machine mode, it will perform auto alignment after XCVR coming out from reset. It will look for pre-defined word alignment pattern configured in Native PHY. " (https://community.intel.com/t5/Programmable-Devices/Will-the-receiver-auto-align/m-p/266156) I tried to manually reset the Custom Phy using the reset controller, but it still does not seem to sync with the pre-defined word pattern. It's as if the sync_sm function is not working at all. I could not find much info on how sync_sm operates. Can someone provide any clues as to what I am missng? Thanks.1KViews0likes3CommentsData transfer between Cyclone V GX Starter Kit and PC
Hello, FPGA newbie here. I'm trying to create an interface between my PC and my Cyclone V GX Starter Kit (https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=830&PartNo=2). The dev kit has a USB UART 232 port and I was able to successfully build a UART interface using intel's RS232 IP (streaming Avalon type) just so I have an understanding of how basic interfaces are created. However, the baud rate max (115200 bauds) is too slow as I am looking for 1+ MB data transfer rate. I'd like to ask if anyone has any recommendation as to how I can accomplish this goal using the ports on my device? What I'd like to ideally do is to be able to send a 16 bit data stream, such as a PC generated Sine wave using Labview software to the FPGA and to send 16 bit data back from the FPGA to the PC. It'd be best if I can do this as simply as possible (e.g. not have to use NIOSII etc.). Any advice would be appreciated. Thanks.Solved1.2KViews0likes3Comments- 1.2KViews0likes0Comments
a/a8/Phase_word_and_bit_align.tcl
The link for a/a8/Phase_word_and_bit_align.tcl is broken in this page: https://community.intel.com/t5/FPGA-Wiki/Cyclone-V-ALTLVDS-Design-Example/ta-p/735385 Can this be updated or can you post the link here? @Angelica_S_Intel @mik_IntelSolved1.2KViews0likes3Comments