New ContributorThe link for a/a8/Phase_word_and_bit_align.tcl is broken in this page: https://community.intel.com/t5/FPGA-Wiki/Cyclone-V-ALTLVDS-Design-Example/ta-p/735385
Can this be updated or can you post the link here?
Occasional Contributor
New ContributorMuch appreciated!
Super ContributorI’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
