Agilex 5E HPS and Linux
Hi. 1. Is there a simple method to run two Linux systems on HPS, i.e.: Linux 1 - 2xA55 and Linux 2 - 2xA76 with different sets of peripherals? 2. Is it possible to use one Ethernet port by these two Linux systems. 3. Is there a simple method for communication between these two Linux systems?
USB Device Issue on Cyclone V / HPS
Hello, Please find below a description of the USB issue we are experiencing with our Cyclone V / HPS board. To test our USB interface, we integrated the TinyUSB library into our existing firmware and enabled FreeRTOS support. Since the Cyclone V is not natively supported, I implemented the missing functions using Altera's hwlib, which we already use in our project (source file attached). The USB is used only in Device mode. I tested the following four configurations: Full-Speed with Slave mode Full-Speed with Simple DMA High-Speed with Slave mode High-Speed with Simple DMA The behavior is identical in all four cases: Connecting our board to a Windows or Linux host is correctly detected. The SETUP transaction is successfully received, and the host receives the device descriptor in response. When the IN transfer complete interrupt is triggered, the USB controller is configured to receive a zero-length packet on OUT0. However, the USB protocol analyzer shows that the device continuously responds with NAK to this packet. The host retries for approximately 5 seconds, but the device keeps responding with NAK. The register values immediately after configuring the reception of the OUT0 packet are: Gotgctl = 0xd00c0 Gintsts = 0x4000020 (PTxFEmp, NPTxFEmp) Gdfifocfg = 0x1f802000 Dctl = 0 Dcfg = 0x8100001 Dsts = 0x18702 Doepctl0 = 0x80008000 Doepint0 = 0 Doeptsiz0 = 0x80000 Grxfsiz = 0x50 After a few milliseconds, I observe that DOEPINT0.NAKINTRPT = 1, which seems to confirm that the device is sending NAKs. However, I do not understand why the OUT packet is not being accepted, since the receive FIFO is not full and both DCTL.GOUTNAKSTS = 0 and DOEPCTL0.NAKSTS = 0.
Agilex 5/3 FreeRTOS Heterogeneous SMP SDK Release
Stable Version: v26.1 Quartus Version: 26.1 Supported devices: Agilex™ 3 and Agilex™ 5 Source: https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v26.1-HSMP Release Date: June 24, 2026 Hello Everyone, A new version of the FreeRTOS SDK for Agilex 5/3 is now available. Apart from other fixes and features, the FreeRTOS port now supports heterogeneous SMP for Agilex™ 5 devices. Visit the GitHub repository for instructions on how to get started. Features and Comments Feature Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP Supported Features Limitations / Known Issues A55 boot Yes Yes Yes Yes Single-core boot, Dual-core SMP, Quad-core SMP (Agilex 5) A76 boot NA Yes NA Yes Single-core boot, Dual-core SMP, Quad-core SMP QSPI boot Yes Yes Yes Yes eMMC boot Yes Yes Yes Yes SD boot Yes Yes Yes Yes NAND boot No No No No Clock Manager Yes Yes Yes Yes API to get clock speed of different blocks Reset Manager Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User-defined and free-running modes UART driver Yes Yes Yes Yes Full-duplex TX and RX DMA not supported (planned for future release) I2C driver Yes Yes Yes Yes Master/Slave mode, standard and fast modes QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase I3C driver Yes Yes Yes Yes Master mode, I3C and legacy I2C devices IBI not supported (planned for future release) SPI driver Yes Yes Yes Yes Master/Slave mode write and read NAND driver No No No No SDM Mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes Standard and HS speeds, SDMMC and eMMC devices, FATFS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP, DHCP, IPv4 and IPv6 USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT Yes NT Yes USB mass storage operation WDT driver Yes Yes Yes Yes Interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver Yes Yes Yes Yes Enable/Disable bridges Reboot Manager Yes Yes Yes Yes Warm/Cold reboot FPGA Manager Yes Yes Yes Yes FPGA configuration Legend: Yes: Feature available and tested No: Feature not available in SDK NA: Not applicable NT: Not tested Note: If you find any issues, please raise an issue on the GitHub repository. For more support and assistance, visit our website.
Support Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGA
Hi Altera Support Team, Greetings from Logic Fruit Technologies. This is Bhanu Pratap and I am working on the project in which we are using Agilex-7 SOC FPGA. Goal: Utilize Agiliex-HPS's capability on a Linux OS to control dynamic features of IP Cores at runtime. Problem Statement: We are facing an issue detecting SignalTap with SoC-based designs for runtime debugging while it's enabled and added from the Quartus project to generate the programming file. Brief Description: We are using Quartus 2025.1.1 and Altera's Agilex-7 Devkit(DKSIAAGI027FA: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit -> 4x F-Tile, Rev C). We downloaded the base GHRD design from Altera's GitHub webpage for the corresponding Quartus version. We are following each step to test GHRD and build generation for the Linux OS. We are using HPS First booting mode, we generated the build without modification and tested it. It's working fine according to the GSRD user guide. We have added a custom AXI4 Slave based CSR module to the HSP Lightweight bus to test basic register read/write using Platform Designer. We regenerated the build and re-tested but we are not getting the expected results so we added SignalTap for debugging. Build is generated using the STP file, programmed, and the OS is booting but it's not detecting SignalTap. This looks more like a process gap. We seek your support to fix this issue. Note: If we use an FPGA design without HPS, we are able to add and detect SignalTap. Seeking for urgent support. Thanks Bhanu Pratap
Agilex 5/3 FreeRTOS SMP Support
Stable Version: v25.4 Quartus Version: 25.4 Supported devices: Agilex™ 3 and Agilex™ 5 Source : https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v25.4-SMP Release Date: March 30, 2026 Hello Everyone, FreeRTOS port for A55/A76 HPS now supports SMP. visit the GitHub page for instructions on how to get started. Features and comments Features Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP (A55 x 2 or A76 x 2) Supported features Limitations/ Known issues A55 boot Yes Yes Yes Yes Single core boot, Dual core SMP A76 boot NA Yes NA Yes Single core boot, Dual core SMP QSPI boot Yes Yes Yes Yes SD boot Yes Yes Yes Yes eMMC boot Yes Yes Yes Yes NAND boot No No No No Clk mngr driver Yes Yes Yes Yes API to get clock speed of different blocks Reset mngr driver Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory to memory transfer Only support memory to memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User defined and free running modes UART driver Yes Yes Yes Yes Full duplex Tx and Rx DMA not supported (Planned for future release I2C driver Yes Yes Yes Yes Master mode write and read Standard and fast modes DMA not supported (Planned for future release I3C driver Yes Yes Yes Yes Master mode write and read i3c and legacy i2c devices IBI not supported (Planned for future release) SPI driver Yes Yes Yes Yes Master mode write and read DMA is not supported QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase NAND driver No No No No SDM mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU enable support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes standard and HS speeds SDMMC and eMMC devices Fat FS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP and DHCP IPv4 and IPv6 support USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT Yes NT Yes USB mass storage operation WDT diver Yes Yes Yes Yes interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver NT Yes NT Yes Enable, Disable Reboot mngr Yes Yes Yes Yes Warm/Cold reboot FPGA manager Yes Yes Yes Yes FPGA configuration Yes: Feature available and tested, No: Feature not available in SDK, NA : Not applicable , NT: Not tested Note: If you find any issues, please raise an issue in the GitHub page. For more support/assistance visit our website .Preloader/U-Boot Compilation Failure
General Background: I'm working with a custom board that has an Altera/Intel Cyclone V, SoC FPGA (5CSEBA6U23, similar to the DE10-Nano development kit). The board is already equipped with all the necessary files for a successful boot sequence from a uSD card (FPGA and the ARM processor (HPS)). The Objective: I want to reconfigure the HPS functionality (Mux) for pins 53 and 54 from their current GPIO to CAN BUS. I need to ensure a successful boot from the uSD card with the updated hardware definition and Device Tree. Issue Description: Preloader/U-Boot Compilation Failure After successfully implementing the changes in Quartus and Platform Designer and after successfully generating the BSP files (bsp-editor), I'm attempting to run the "make" command to build the Preloader/U-Boot image. The process starts and creates the uboot-socfpga directory, but the compilation consistently fails with several errors, and the final boot image is not updated. Extension of the successfully completed steps: I've modified the Platform Designer (Qsys) mux functionality to reconfigure the HPS peripheral pins (GPIO53-GPIO54) for CAN BUS functionality. I've integrated the new HPS component into the top-level VHDL project. I've Generate a full VHDL compilation in Quartus. Using the "SoC EDS Command Shell", I launched the BSP-Editor and loaded the updated "settings.bsp" file. After generation, the "hps_isw_handoff" and "generated" directories were updated. I have manually verified the output files (pinmux_config.h) to confirms that CAN1 is now correctly configured in the pin multiplexing settings. What should I do?
Arria 10 SoC – USB devices always enumerating as Full-Speed (Yocto 4.1, dwc2)
Hello, My name is Ángel and I am currently working with an Intel SoC FPGA Arria 10. I am trying to connect an Intel RealSense SR300 camera to my system, but I am experiencing USB speed negotiation issues. Environment: Platform: Intel SoC FPGA Arria 10 OS: Linux (custom image built with Yocto 4.1 Langdale) USB driver: dwc2 librealsense built with -DFORCE_RSUSB_BACKEND=ON When I connect the RealSense SR300 camera, the USB link does not negotiate correctly and the device is always enumerated as Full-Speed (12M) instead of High-Speed or SuperSpeed. At first, I suspected a problem with the USB 3.0 connector of the SR300. However, when I tested with a standard USB 2.0 webcam, I observed exactly the same behavior: the device is still enumerated only as Full-Speed (12M). This suggests the issue is likely related to the USB controller configuration on the Arria 10 rather than the camera itself. System Output lsusb -t: /: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=dwc2/1p, 480M |__ Port 1: Dev 2, If 0, Class=Vendor Specific Class, Driver=, 12M |__ Port 1: Dev 2, If 1, Class=Audio, Driver=, 12M |__ Port 1: Dev 2, If 2, Class=Audio, Driver=, 12M dmesg: [ 204.765768] usb 1-1: new full-speed USB device number 2 using dwc2 Yocto local.conf: MACHINE = "arria10" DISTRO_FEATURES:append = " systemd vfat" DISTRO_FEATURES:remove = " sysvinit" VIRTUAL-RUNTIME_init_manager = "systemd" IMAGE_INSTALL:append = " kernel-module-uvcvideo" KERNEL_MODULE_AUTOLOAD += "uvcvideo" IMAGE_INSTALL:append = " \ packagegroup-core-boot \ pciutils \ usbutils \ v4l-utils \ i2c-tools \ librealsense2 \ " EXTRA_OECMAKE:append:pn-librealsense2 = " -DFORCE_RSUSB_BACKEND=ON" Any guidance would be greatly appreciated.
