NIOS II "Verify failed" for on-chip memory 128k
Hello! I'm using a Cyclone 10LP FPGA 10CL055YU484I7G FPGA. I have a 11k size program for NIOS II. I have a large on chip RAM (because I have a larger program which I want to use later) of 128k. Everything compiles and links OK. But when I try to download the program I get a "Verify failed between address 0x20000 and 0x2FFFF". The 128K memory is located 0x20000 to 0x3FFFF If I reduce the RAM to 32K, for example, everything works great!!. The initialize memory content option is turned on for the memory The BOOT RAM starts at 0x00000 If I download a bigger program (117k), I still get the same error. Thanks
NIOS-V QSYS Warning Properties (associatedClock) have been set on
Hello, I have a really basic setup of a NIOS V system, but get Warnings in QSYS (using Quartus 25.1 Standard) about Properties of associatedClock: System: Warning: Warning: nios_subsystem.intel_niosv_m_0: Properties (associatedClock) have been set on interface reset - in composed mode these are ignored Warning: nios_subsystem.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface instruction_manager - in composed mode these are ignored Warning: nios_subsystem.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface data_manager - in composed mode these are ignored Questions: What is "composed mode" and how can I control it? There is no NIOS Parameter associated with it This appears in a basic setup simply by adding NIOS V to the system. How do I get rid of this warning? best regards Fabian
DK-DEV-AGI027-RA: JTAG chain broken after Nios V Hello, FPGA recovery fails
Hello, I am using the following board and host environment: Board: Agilex 7 FPGA I-Series Development Kit, DK-DEV-AGI027-RA Serial number: 8100604 Quartus Prime Pro: 25.3.1 Host OS: Windows 11 Pro Before this issue, the board was working normally with CXL ED and PCIe designs. Issue summary After successfully running a modified version of the "Nios V Hello" tutorial design (SOF + ELF) on this kit, Quartus Programmer can no longer detect the JTAG chain reliably. "Auto Detect" fails, and the JTAG Chain Debugger reports unknown devices and possible JTAG signal issues. Steps and observations 1. I modified the Nios V Hello tutorial design (SOF + ELF), including pin assignments and power management & SmartVID assignments, to match DK-DEV-AGI027-RA. Programming completed successfully, and I confirmed the expected "Hello" output. After that first run, I attempted to download an updated SOF, but Quartus Programmer "Auto Detect" failed. JTAG Chain Debugger screenshot: Programmer/Debugger log: !Error: JTAG chain problem detected !Error: TDI connection to the first detected device UNKNOWN_00000001 might be shorted to GND !Error: The TCK and TMS connections to the device before the first detected device UNKNOWN_00000001 might have a problem !Info: Detected 2 device(s) !Info: Device 1: UNKNOWN_00000001 !Info: Device 2: UNKNOWN_020D10DD Recovery attempts and results 2. Connected an external USB-Blaster II to J10, set SW8.3 = ON, and completed MAX10 recovery successfully. 3. Set SW8.3 = OFF to attempt FPGA recovery. Quartus Programmer Auto Detect still failed. 4. Loaded the predefined fpga_recovery.cdf and attempted to program AVSTX8.pof, but it failed with: Error(209062): Flash Loader IP not loaded on device 2 Error(209012): Operation failed 5. Set SW8.2 = ON to remove the FPGA from the JTAG chain, then successfully programmed AVSTX8.pof into QSPI. 6. Set SW8.2 = OFF again, but Auto Detect still failed. 7. Removed the external USB-Blaster II and tried the embedded JTAG interface. Auto Detect still failed. Questions. Are there additional recommended steps beyond MAX10 recovery and programming the recovery POF to QSPI (for example, specific switch combinations, a required full power-cycle sequence, or other board-level recovery steps)? If MAX10 recovery completes but JTAG remains broken on both external and embedded JTAG, does this suggest a likely hardware issue (JTAG path, FPGA, or related circuitry) that requires RMA? Is there anything in the Nios V Hello tutorial flow that could plausibly cause this condition (for example, power management settings, pin assignments, or JTAG-related settings)? If needed, I can share additional logs, exact switch settings, and any other diagnostics you recommend. Thanks.LPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 Pro
Hello, I have a simple design for Agilex 5, using NIOS V/g and EMIF IP with LPDDR4 memory. I have the NIOS V instruction and data manager ports connected to the EMIF IP. Design compiles Ok. But when I create a BSP, in the linker section, there is not a memory device for the LPDDR4. In this thread, a similar problem seems to be mentioned - issue-with-bsp-creation-for-nios-vm-using-lpddr4-on-agilex-5-quartus-24-1--24-3 Does it mean that Address Span Extender IP must be used in order to have the LPDDR4 show in the linker script section, as an available memory device?
USING SIGNAL TAP TO MONOTOR AVALON_BUS WITH NIOS DESIGN
hii i need to use signal tap to see what's happening on avalon bus , i have a qsys system that is working fine , its the remote update example , and when i add a signal tap file and add for example the avalon bus signals the connects to the on chip flash ip , and i try to write the cfm0 the signal tap does not work . i put the trigger on a rising edge of a avalon_write and nothing seems to happen , i be glad for help :)licensing.altera.com never worked
Hi Altera, I need to apply Nios V free license, https://licensing.intel.com went to https://www.altera.com/SSLC , I signed in successfully, however the FPGA Self Service Licensing Center.never worked, I got the error "You do not currently have access to this site." for few weeks, see picture below. Please help fix this issue. Thanks.
DE23-Lite + Quartus Pro 25.1 + Nios V/g: no Nios V instance, no JTAG UART
Hi, I’m working on a Terasic DE23-Lite board (Agilex 3 A3CZ135BB18AE7S) using Quartus Prime Pro 25.1, and I’m seeing a runtime debug/service issue that I have not been able to resolve. System details: Board: Terasic DE23-Lite FPGA: Agilex 3 A3CZ135BB18AE7S Quartus Prime Pro: 25.1 CPU in Platform Designer: Nios V/g Project started from the Terasic SDRAM_Test_NiosV / golden_top example USB-Blaster III is detected normally as DE23-Lite [USB-1] What works: quartus_pgm programs the .sof successfully jtagconfig sees the board and FPGA in the JTAG chain Simple RTL-only hardware tests work CLOCK0_50-driven LED blink works KEY0-driven LED test works So basic board programming, raw JTAG visibility, and simple user logic are all working. What does not work: niosv-download fails with: "There are no devices with valid Nios V instance(s)" "ERROR: Failed to generate OpenOCD config file." juart-terminal fails with: "There are no JTAG UARTs available which match the --device and --instance options you provided." In System Console, the following all return nothing: get_service_paths device get_service_paths master get_service_paths processor get_service_paths jtag_debug SignalTap also does not enumerate at runtime and reports that the device needs to be programmed / instance not found, even after compile and program. Important points: The generated Platform Designer system does include Nios V/g debug-related logic and JTAG UART in the generated HDL. The top-level does instantiate the generated nios_system. The QSF includes the Qsys system. The fit report shows SignalTap content present in the fitted image. So this does not look like a missing-instance-in-the-design problem. It looks more like raw JTAG chain works, but no higher-level runtime services enumerate after configuration. One thing I found: In the example golden_top.v, the Nios system clock connection had a typo: .clk_clk(CLOCK1_51)instead of a real clock signal. I corrected that and also tested CLOCK0_50. That did not resolve the no-instance / no-JTAG-UART / no-service-paths issue. Another issue I found and fixed: There was a stale on-chip memory init reference to ram.hex: "Cannot find Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) C:/fpga/SDRAM_Test_NiosV/ram.hex -- setting all initial values to 0." I removed that stale reference. It did not fix the runtime service visibility problem. Current question: Has anyone seen a case on DE23-Lite / Agilex 3 / Quartus Pro 25.1 where the JTAG chain is visible and programming succeeds, but Nios V instances, JTAG UART, System Console service paths, and SignalTap all fail to enumerate at runtime? I’m looking for guidance on what layer to check next: JTAG service / SLD runtime visibility Agilex 3 user-mode debug exposure board/project configuration settings Quartus 25.1-specific issue anything DE23-Lite-specific in the Terasic example flow Any suggestions would be appreciated. Thanks, Steve
AshlingRISCFree IDE Build system: 'source directory does not appear to contain CMakeLists.txt"
Hello Altera Gurus, I am now having much trouble building my projects with the AshlingRISCFree IDE using a NIOSV/m processor on a MAX10 FPGA targeted at a MAX10 Development kit. I am using Quartus Standard edition 25.1 on a Windows 10 PC. The process i am following is this: I created an FPGA top level System Verilog file for a new MAX10 Project. created a Qsys Platform which has a NIOSV/m processor connected to a onchip RAM for program storage and a onchip RAM for the DMA data. Added one mSGDMA engine for transmit data operations Added a second mSGDMA engine for receivedata operations Added two RAM onchip memories for the DMA decsriptors and wired up everything created the address map and interrupt mapping saved and generated the Qsys platform In the top level SV file is loopback the Tx -> RX for the two mSGDMAs Used the niosv-bsp-editor in a niosv console to created a BSP using the Qsys sopcinfo file Generated the BSP, created a simple C main application to configure the mSGDMAs and NIOSV/ m processor etc. Imported both the HAL_BSP and HAL_APP folders using: 'Import NIOS-V CMake Project... In the AshlingRSICFree IDE i can successfully run a 'Build all' and compile the HAL_BSP. BUT When i select the hal_app folder and try to build the Project i get these error messages: 17:37:20 Buildscript generation: hal_app::Default in D:\VAREX_mSGDMA_Eval\software\hal_app\build\Default cmake -DCMAKE_EXPORT_COMPILE_COMMANDS:BOOL=ON -G "Unix Makefiles" "D:\\VAREX_mSGDMA_Eval\\software\\hal_app" CMake Warning: Ignoring extra path from command line: "D:\VAREX_mSGDMA_Eval\software\hal_app" CMake Error: The source directory "D:/VAREX_mSGDMA_Eval/software/hal_app" does not appear to contain CMakeLists.txt. Specify --help for usage, or press the help button on the CMake GUI. Problems : Description Resource Path Location Type CMake Error: The source directory "D:/VAREX_mSGDMA_Eval/software/hal_app" does not appear to contain CMakeLists.txt. hal_app de.marw.cdt.cmake.core.internal.CMakeErrorParser CMake Problem cmake exited with status 1. See CDT global build console for details. hal_app de.marw.cdt.cmake.core.internal.BuildscriptGenerator Buildscript Generation Problem Looking at the hal_bsl folder i can see the CMakeLists.txt is present, it is not present (automatically anyway) in the hal_app folder. I assume it would be if it was part of the BSP generate flow, but it ins't there so i assumed it shouldn't be there (in the hal_app folder i mean). Even if i add it manually then try to do a project build again i then see an error message saying the CmakeCache.txt file has not been created. This seems like a big tools flow mess to me. The Project is automatically setup to use a CMake Compile and CMake Build flow. But its not working. I am trying to use the AshlingRISC IDE GDB Debugger to load my ELF file to the NIOSV processor to allow me to debug my project, but of course because i can't even build it this is impossible. I have tried using niosv cli commands to build my ELF file ...and they seem to work, which means the AshlingRISC IDE is the culprit in the failed IDE build process: Here are my NIOSV cli commands : mSGDMA Test: $ niosv-app --bsp-dir=D:/VAREX_mSGDMA_Eval/software/hal_bsp --app-dir=D:/VAREX_mSGDMA_Eval/software/hal_app --srcs=D:/VAREX_mSGDMA_Eval/software/hal_app/msgdma_loopback.c $ cmake -S D:/VAREX_mSGDMA_Eval/software/hal_app -B D:/VAREX_mSGDMA_Eval/software/hal_app/build -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug $ make -j4 -C D:/VAREX_mSGDMA_Eval/software/hal_app/build After i try and fail to do a project build i can also no loner clean this project, it gets stuck in red with the same error. The only way i can get it back to the start state is : File -> Restart ...this is not great !! Does anybody know why i get these errors and how to fix them please ? : Here i have also linked to an older post here in the knowledge base Claiming that "This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4. and later". This appears to be NOT the case though :) Why does CMake Error: The source directory "<project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN" does not contain CMakeLists.txt. when compiling the Nios® V processor application in Command Line Interface? | Altera Community - 338917 NOTE: I have attached 3 screenshots, 2 show the output from the NIOSV CLI when i run the 3 compile commands. The third one shows what happens when i try to load the ELF file which was created after the 3 Compilation steps run to completion. It looks like the GDB debugger detects the NIOSV/m processor (the 1 hard message) and then promptly crashed during part of the boot process. Does anybody have any ideas about why that might be and what is going on please ? Thanks for any help, Dr Barry H
