nios architecture

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NIOSV/g with FPU: inconsistent calculation results
I'm using a NIOSV/g with FPU enabled in a MAX10 project. The project involves heavy use of float point calculations, hence the need for the FPU. I noticed some occasionally inconsistent results in this program and started debugging - assuming this was a bug in my code. However I was able to run my code in a simulator and on a different RISCV microcontroller and everything worked flawlessly. I also disabled the FPU in the NIOSV design and again the code ran fine. In order to recreate the problem, I created a basic project with just the NIOSV, some RAM and the JTAG-Uart. I also wrote a tiny C program to stress test the FPU. The results of this show that again, the FPU is producing incorrect results. I've attached a screenshot of the Platform Designer design. I'm running the design at 75Mhz and the design meets timing requirements. Here is the code I ran. Note that I have interrupts disabled to be sure this isn't a context switching issue. I also did not wrap the calculations into a function so I could more easily view the various calculation results in the debugger. This code works as expected when using a soft-FPU. When using the NIOSV FPU, results are inconsistent. I've attached a screenshot of one failed cycled. You can see that a1 and b1 are not equal. #include <stdint.h> #include <math.h> #include "sys/alt_stdio.h" static void fpuTest(void) { int fail_count = 0; int iteration = 0; while (1) { float a0 = (float)iteration * 0.001f; float a1 = 1.1f * sinf((float)iteration * 0.1f); float a2 = 2.2f / (1.0f + (float)iteration * 0.0001f); float a3 = sqrtf(3.3f + (float)iteration); float a4 = powf(4.4f + (float)iteration, 1.1f); float a5 = logf(5.5f + (float)iteration + 1.0f); float a6 = 6.6f * cosf((float)iteration * 0.05f); float a7 = 7.7f + tanf((float)iteration * 0.02f); float result_a = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7; float b0 = (float)iteration * 0.001f; float b1 = 1.1f * sinf((float)iteration * 0.1f); float b2 = 2.2f / (1.0f + (float)iteration * 0.0001f); float b3 = sqrtf(3.3f + (float)iteration); float b4 = powf(4.4f + (float)iteration, 1.1f); float b5 = logf(5.5f + (float)iteration + 1.0f); float b6 = 6.6f * cosf((float)iteration * 0.05f); float b7 = 7.7f + tanf((float)iteration * 0.02f); float result_b = b0 + b1 + b2 + b3 + b4 + b5 + b6 + b7; // Check if result is consistent (should be identical) if (fabsf(result_a - result_b) > 1e-6f) { alt_printf("FPU test failed at iteration %x\n", iteration); fail_count++; } iteration++; } } int main(void) { // Make sure interrupts are disabled __asm volatile ( "csrc mstatus, 8" ); fpuTest(); while (1); return 0; } Can someone help me investigate what could be wrong here? Could there be an issue in the FPU itself?
Broddo
6 months ago Place Nios® System
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read/ write with IORD_32DIRECT and IOWD_32DIRECT problem
Hi All, I am using the quartus pro 23.4 with Asling 23.4.1 I have used the avalon_slave bus in my own module. After building the BSP and I try to run the IORD_32DIRECT (base_address) or even IOWD_32DIRECT(base_address, data) and I found there are 8 read/ write pulse when I use the signal tap analyser to check on it. See anyone have idea on this issue. Thank you very much. Best regards, Paul
Paul83
2 years ago Place Nios® System
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Implementing many Nios® V cores on Agilex™ 7
Table of Contents Introduction Environment Configuration (HW) Configuration (SW) Mass Implementation Multicore Debugging Conclusion Note: This article is an English translation of this Japanese article by Macnica. Please refer to the original article for updates. Introduction The attention to RISC-V has been increasing year by year, and it seems that many manufacturers are developing based on RISC-V. The Nios® V I use this time is also one of the RISC-V based processors, and it is a softcore processor developed by Intel. This article is an experimental article about implementing Nios® V to the limit on Agilex™ 7, thinking about doing something interesting with RISC-V. Environment This time, since we are using Intel FPGA and Nios® V, we will use the following: Intel® Quartus® Prime Pro Edition Software Version 22.2 for Windows Ashling* RiscFree* IDE for Intel® FPGAs We will use the following for Agilex™ 7: Agilex™ 7 FPGA F-Series Development Kit (P-Tile and E-Tile) Configuration (HW) This time, to implement many Nios® V, we have created a submodule with Nios® V, and are instancing that module in the top level. The configuration of the submodule includes: Nios® V/m processor On Chip RAM JTAG-UART These three are the minimum requirements for operation confirmation. The top level includes: CLK Reset Submodule (Nios® V) ISSP Reset You may not be familiar with ISSP, but understand that we are using HW logic with ISSP to toggle the Reset because the development kit used this time does not have a reset button for FPGA. The block diagram of this configuration is as follows. (Orange is Bridge, and purple is IP, color-coded.) In this configuration, the On chip RAM for Nios® V execution memory is generated with 128kByte. For details, please refer to the capture of the Platform Designer in "Mass Implementation". This time, since we will not perform a standalone operation confirmation, we have constructed it to only run the elf file in RAM with a debugger without considering detailed settings such as Reset Vector or Boot methods for each Nios® V. Configuration (SW) The software is a simple program that outputs to the JTAG console. Since we implement multiple Nios® V, it is better to write the program so that the outputs from different cores can be distinguished. Please refer to the final outputs at the end of section Multicore Debugging. Mass Implementation This configuration is created in Platform Designer. Since we only need to instance the submodules in the top level, we are lucky that the top level remains clean, although it took time to generate. First, let's check with only one Nios® V. As explained earlier, it appears that only one Nios® V submodule is implemented in the Platform Designer system. Below is the top level system diagram (the red frame is the Sub module). This is the Sub Module (the red frame is Nios® V/m processor). The compilation result is below. Even though we used 128kB Onchip RAM, it is still only 1% utilized. Next, let's try with 10 units. To make it easier later, we have created a submodule that implements 10 submodules and instance it in the top level. Below is the compilation result. Roughly, the RAM block usage is 1% per Sub module. Let's go bold and implement 100 units. We barely managed to implement it! It's okay to implement 100 units!! Although we think we can implement a few more, as the RAM resources are over 90%, we will settle with 100 units for now. Multicore Debugging Finally, I would like to write about debugging when implementing multiple units. For the Nios® V development environment, we use Ashling* RiscFree* IDE for Intel® FPGAs introduced in Chapter 2. It can be downloaded together with Intel® Quartus® installer, so please install it together. Here, I will omit the steps for launching Ashling* RiscFree* IDE for Intel® FPGAs and importing the project. The build process was referenced from the article below: Development Procedure for Nios® V Projects using Ashling* RiscFree* IDE for Intel® FPGAs After you have built the projects, first create a Debug configuration for each CPU. You can select which CPU to create for from the Core selection in the Debugger tab, as shown below. After setting and creating the Debug configuration for each CPU, group them with Launch Group to execute them simultaneously. This completes the Debug configuration. Next, prepare the console output destination. This time, due to screen display limitations, we will display the output in each Nios® V command shell. Launch the Nios® V command shell for each CPU and execute the following command: #juart-terminal -c <change for each CPU> -d <device number> -i <instance number> juart-terminal -c 1 -d 0 -i 0 With this command, each Command shell will be linked to the JTAG console. (The last number in Core selection corresponds to the argument of -i.) Select the Group created earlier and press Debug. By default, it will break at the start of the main function, so you can add breakpoints, check register and variable values for each source to debug. The execution result this time is shown below. We captured the situation where the JTAG console is running simultaneously. Conclusion This time, I implemented many Nios® V just for fun, but it took a lot of time for tasks such as compilation time and Platform Designer hierarchy design. It was quite difficult for an article started with a light heart. However, since I think there are few people who actually perform this configuration, I hope you will find the multicore debugging part helpful. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Nios is a trademark of Intel Corporation or its subsidiaries.
symmt_Intel
2 years ago Place Nios® System
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Cyclone 10 GX Nios V: TSE with mSGDMA Not Responding to Ping
Hello , I am using a Cyclone 10 GX with Nios V and the Micrium MicroC/OS-II operating system. My setup includes the Triple-Speed Ethernet Intel FPGA IP paired with the Modular Scatter-Gather DMA Intel FPGA IP, connected to a DP83620 PHY IC. Problem Description: In my implementation, the auto-negotiation completes successfully, and the link is established as indicated by the PHY status registers. I have configured an IPv4 address, subnet mask, and gateway using NetIPv4_CfgAddrAdd. Additionally, the socket() creation, bind(), and listen() calls in my socket server task all succeed without errors. However, the system does not respond to ping requests from a connected PC using the assigned IP address. Key Information: The Ethernet MAC and PHY configuration seem correct: Auto-negotiation and link establishment indicate that hardware connections are likely fine. The MAC and IP address settings are successfully applied. The Modular Scatter-Gather DMA is initialized and configured, but there might be a gap in how the RX/TX buffers and descriptors interact with the network stack. Debugging Steps Taken: Verified MAC, PHY, and DMA initialization logs. Confirmed that the socket(), bind(), and listen() functions in the SocketServerTask return no errors. Observed proper PHY register behavior, including link status and speed/duplex negotiation. If anyone has experience with a similar setup or can offer suggestions on how to debug further or resolve this issue, I would greatly appreciate your input!
Paul36
11 months ago Place Nios® System
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Why my HelloWorld program is not working in Nios V/g while working perfectly in Nios V/m?
Hi, I migrated a golden system reference design (GSRD) for the Terasic DE0-Nano board that is based on a Nios II/e processor to another GSRD for the same board but based on a Nios V/m processor. A simple HelloWorld program works perfectly in a system integrated by: Nios V/m + SRAM on chip memory + JTAG UART controller. However, the same HelloWorld program does not work when the Nios V/m core is swapped by a Nios V/g processor. These are the hw/sw elements used for the practical experience: - OS: Windows 10 - FPGA software for HW compiling: Quartus Prime 23.1 standard - BSP & SW Compiling and HW/SW Programming framework: Nios V Command Shell - Board: Terasic DE0-Nano - FPGA device: Cyclone IV E Please, could I have any help? Attached files: - DE0_Nano_Basic_Computer.qpf (Quartus Prime) - nios_system.qsys (Platform Designer, NiosV/g) - DE0_Nano_Basic_Computer.v - settings.bsp (Nios V/g) - HelloWorld.c During the hardware compilation of the Nios V/g version, some warnings were generated in Quartus. These warnings were not generated for the Nios V/m version. Info (12128): Elaborating entity "nios_system_intel_niosv_g_0" for hierarchy "nios_system:NiosII|nios_system_intel_niosv_g_0:intel_niosv_g_0" Info (12128): Elaborating entity "nios_system_intel_niosv_g_0_hart" for hierarchy "nios_system:NiosII|nios_system_intel_niosv_g_0:intel_niosv_g_0|nios_system_intel_niosv_g_0_hart:hart" Warning (10036): Verilog HDL or VHDL warning at nios_system_intel_niosv_g_0_hart.sv(274): object "core_ci_f7" assigned a value but never read Info (12128): Elaborating entity "niosv_g_core_nios_system_intel_niosv_g_0_hart" for hierarchy "nios_system:NiosII|nios_system_intel_niosv_g_0:intel_niosv_g_0|nios_system_intel_niosv_g_0_hart:hart|niosv_g_core_nios_system_intel_niosv_g_0_hart:core_inst" Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(303): object "rd_reg_c" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(314): object "wr_fpr_en" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(315): object "wr_fpr" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(316): object "wr_fpr_data" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(327): object "W_instr_valid" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(334): object "M0_nxt_seq_pc" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(356): object "W_instr_word" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(464): object "M0_mem_op" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(470): object "E_jmp" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(471): object "E_ebreak_instr" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(472): object "E_ecall_instr" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(534): object "D_rs3_fpr_val" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(538): object "E_rs1_fpr_val" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(542): object "M0_rs1_gpr_val" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(548): object "M0_multicycle_instr_done" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(618): object "I_expn_type" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(623): object "W_expn_type" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(764): object "M0_instr_incorrect" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(767): object "M0_itag_incorrect" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(796): object "M0_ecc_rs1" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(797): object "M0_ecc_rs2" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(800): object "ecc_src" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1049): object "I_ebreak_instr" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1050): object "I_ecall_instr" assigned a value but never read Warning (10230): Verilog HDL assignment warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(812): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1236): truncated value with size 4 to match size of target (2) Warning (10763): Verilog HDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1698): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness Warning (10270): Verilog HDL Case Statement warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1698): incomplete case statement has no default case item Warning (10763): Verilog HDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1711): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness Warning (10270): Verilog HDL Case Statement warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1711): incomplete case statement has no default case item Best regards, Domingo.
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Benitez__Domingo
2 years ago Place Nios® System
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Problem writing the NIOS II program to the EPCS controller.
I have a problem writing the NIOS II configuration and program to the EPCS controller. I've read the entire Internet on this topic and 70 posts on this forum. I've tried everything that's written here. My configuration. Chinese board OMDAZZ Cyclone 4E CPLD EP4CE6E22C8. I wrote a simple program that works in OnchipRAM. It blinks the LED and displays information on the LED indicator. This program was store to the OnchipRAM image and converted to a JIC file. It works. The EPCS controller is connected to the data bus, instruction bus, reset (including from JTAG) and PLL output 12 MHz. The EPCS base address is 0x8002000. NIOS II reset is assigned to the same address 0x8002000. Exception Vector is in OnchipRAM. The linker is configured to generate code in OnChip. allow_code_at_reset and the other 4 keys are disabled. log_port is disabled. In the linker settings I also see the correct reset address on the EPCS base. I am using Quartus II 13.1. I saw that there is a problem for Quartus II 13.0: Boot from Quad Serial Configuration(EPCQ) and Serial Configuration (EPCS) https://www.intel.com/content/dam/support/us/en/programmable/kdb/rd11122013-865/nios-ii-boot-from-epcq-and-epcs-in-quartus-ii-13-0.pdf Is this problem still present in Quartus II 13.1? Is there a patch for this? I read that EPCS boot only works with NIOS II/f processors. Is this true? https://community.intel.com/t5/Programmable-Devices/Nios-II-EPCS-booting-problem/m-p/113883#M32137%3Fwapkw=Epcs I tried the steps described here: https://community.intel.com/t5/Programmable-Devices/Nios-II-EPCS-booting-problem/m-p/113883#M32137%3Fwapkw=Epcs https://community.intel.com/t5/Programmable-Devices/Nios-Boot-up-from-EPCS/m-p/166705#M52307%3Fwapkw=Epcs https://community.intel.com/t5/Nios-V-II-Embedded-Design-Suite/Problem-booting-program-from-EPCS-flash-and-running-from-SRAM/m-p/142473#M38487%3Fwapkw=Epcs When generating nios_load1.sopcinfo I get two warnings: Warning: nios_load1.epcs_flash_controller_0: epcs_flash_controller_0.external must be exported, or connected to a matching conduit. Warning: nios_load1.epcs_flash_controller_0: Interrupt sender epcs_flash_controller_0.irq is not connected to an interrupt receiver I think it's not critical. I know several ways to get a HEX file. This is the only way to get a working file. I took this method from mem_init.mk. elf2hex NIOS_LED_SDRAM_APP.elf 0x08008000 0x0800cfff --width=32 --little-endian-mem --create-lanes=0 ../../output/EPCS_w.hex --verbose I inserted this file as an OnchipRAM image to check. It works. For write to EPCS, I converted the EPCS_w.hex file to the HEX byte format as described on the forum: Set Assignment -> Srtting -> More Setting -> set the Reading Or Writing HEX in byte adrresable mode key to OFF Load the EPCS_w.hex file to Kvartus Set Assignment -> Srtting -> More Setting -> set the Reading Or Writing HEX in byte adrresable mode key to On Save the EPCS_w.hex file. Then I loaded the file EPCS_w.hex into the converter to get the JIC file (also load SOF file). The converter created a JIC file with a report in SDRAM_LED.map Page_0 0x00000000 0x00023038 EPCS_sw.hex 0x00023039 0x00025DA0 Tried different offsets as recommended on the forum. Turned off and on SOF file compression. Doesn't help. Another way to get a HEX file sof2flash --input=../../output/NIOS_II_My.sof --output=hw.flash --epcs nios2-elf-objcopy --input-target srec --output-target ihex hw.flash ../../output/EPCS_hw.hex --verbose elf2flash --input=NIOS_LED_SDRAM_APP.elf --output=sw.flash --epcs -after hw.flash --verbose nios2-elf-objcopy --input-target srec --output-target ihex sw.flash ../../output/EPCS_sw.hex --verbose creates a HEX file that does not work even as an image in OnchipRAM. Can you tell me why? What did I do wrong here? I'm confused with the nios_load1_epcs_flash_controller_0_boot_rom.hex file. It is created when generating nios_load1.sopcinfo in the sopc\nios_load1\synthesis\submodules folder. But when using the mem_init_generate script in the mem_init/hdl_sim folder, this script also creates the same file. But if disable allow_code_at_reset in the linker and 4 keys below, this file consists of only one line - the end of the file. As far as I understand, the nios_load1_epcs_flash_controller_0_boot_rom.hex file is an image of the ROM disk of the EPCS controller. Could it be that when generating nios_load1.sopcinfo, the wrong file is created or should I create this file myself to replace the generated one? When programming Flash Programmer gives an error Info: No EPCS registers found: tried looking at addresses Info: 0x08002000, 0x08002100, 0x08002200, 0x08002300 and 0x08002400 Error: Error code: 8 for command: nios2-flash-programmer "E:/Q_Project_03_03/NIOS_LED_SDRAM/Software/NIOS_LED_SDRAM/flash/NIOS_II_My_epcs_flash_controller_0.flash" --base=0x8002000 --epcs --sidp=0x80010A0 --id=0x12345678 --timestamp=1741934460 --device=1 --instance=0 '--cable=USB-Blaster on localhost [USB-0]' --program --verbose However, if program the JIC file, the recording and checking are successful, the hardware works, but NIOS II does not start. I ask for help back up this situation me led to a dead end and not to see a solution. I"m have experience electronics and programming. I will understand even two words where I was wrong. Sorry for my bad English
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Megavolt91
9 months ago Place Nios® System
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using fprintf with stdout parameter in NIOS2
Hello. If I want to write alternative output string to JTAG_UART and NIOS_UART can I use the function fprintf using the distenation as the first parameter? Is it possible to chose the stdout during run or it must be define fix, and if I can what should be the parameter to place in for JTAG_UART & NIOS_UART? Thanks
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Bar
3 years ago Place Nios® System
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How is Nios V's MHARTID csr register assigned a determined value?
Hello, When multiple instances of the Nios V processor are integrated into a multiprocessor SoC, access to the MHARTID csr register when they execute concurrently is needed to identify the hardware thread. The Parameters tab of the configuration screen for Nios V in the Platform Designer tool does not allow assigning any value to the MHARTID register. For Nios II, there is a parameter for manually assigning the CPUID control register value, but for Nios V I do not see a similar parameter. Then, my question is: how is Nios V's MHARTID csr register assigned a determined value? Regards, Domingo.
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Benitez__Domingo
12 months ago Place Nios® System
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Processor nios v
Hello good morning. I need to use the nios V processor to generate an interrupt, it's a simple project, but it's getting a bit complicated. I wanted to know if anyone has any similar examples that they could share to have a guide base, since I am not finding much related to the subject on the web. sorry if my english is bad. Thank you so much.
spar
3 years ago Place Nios® System
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Issue with SRAM and SDRAM in NiosV
Hey everyone. I am a student currently working on a project with niosv processor and de10 lite fpga. For this project i have Ashling Riscfree IDE to write the code. I currently have two designs and both of them cause errors related to SRAM in one and SDRAM Controller in another. In platform designer i had a design with IPs like niosv, jtag, sram, led_pio, uart_fifo. But then recently i added sdram controller and removed sram. Problems: 1) Both of the designs compile successfully in quartus but i get errors in Ashling IDE. In SRAM Version, I was getting errors that my .bss, .text and .rwdata segments weren't in the region of sram and also there was a memory overflow by around 30 KB. All these errors occurred while i was using printf function. I checked the linker script and all of those were linked with sram. So i guess thats correct. The thing is: Whenever i was doing minimal use of printf function without line breaker (\n) inside the printf function, i was getting those errors. And, also using many printf function (around 7-10) with the line breaker, also resulted the same errors. My Sram has 128 KB and should be enough for my program. 2) Having that problem i switched my design from sram to sdram controller. Here i have PLL100 for the clock generator and has phase shift of - 3ns to 3ns. Niosv, jtag, sdram conrroller, uart_fifo and led_pio are used in this design. The problem with this version is that i dont get error that i had with sram cause my space went up from 128KB to 64 MB, i guess. But another error has come up and that being, my simple hello world wont get printed properly. Whatever i print with or without line breaker (\n) with the printf function, only alternate characters get printed. For example, if i print "Hi Niosv", i get "iNov". Line space between the words is also counted as a character. Solution for either of these versions is acceptable, so i would really appreciate it, if you guys could give some tips or help to solve it. Thanks in advance guys.
Kaazi32
2 years ago Place Nios® System
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