Occasional ContributorWhy my HelloWorld program is not working in Nios V/g while working perfectly in Nios V/m?
Hi,
I migrated a golden system reference design (GSRD) for the Terasic DE0-Nano board that is based on a Nios II/e processor to another GSRD for the same board but based on a Nios V/m processor.
A simple HelloWorld program works perfectly in a system integrated by: Nios V/m + SRAM on chip memory + JTAG UART controller.
However, the same HelloWorld program does not work when the Nios V/m core is swapped by a Nios V/g processor.
These are the hw/sw elements used for the practical experience:
- OS: Windows 10
- FPGA software for HW compiling: Quartus Prime 23.1 standard
- BSP & SW Compiling and HW/SW Programming framework: Nios V Command Shell
- Board: Terasic DE0-Nano
- FPGA device: Cyclone IV E
Please, could I have any help?
Attached files:
- DE0_Nano_Basic_Computer.qpf (Quartus Prime)
- nios_system.qsys (Platform Designer, NiosV/g)
- DE0_Nano_Basic_Computer.v
- settings.bsp (Nios V/g)
- HelloWorld.c
During the hardware compilation of the Nios V/g version, some warnings were generated in Quartus. These warnings were not generated for the Nios V/m version.
Info (12128): Elaborating entity "nios_system_intel_niosv_g_0" for hierarchy "nios_system:NiosII|nios_system_intel_niosv_g_0:intel_niosv_g_0"
Info (12128): Elaborating entity "nios_system_intel_niosv_g_0_hart" for hierarchy "nios_system:NiosII|nios_system_intel_niosv_g_0:intel_niosv_g_0|nios_system_intel_niosv_g_0_hart:hart"
Warning (10036): Verilog HDL or VHDL warning at nios_system_intel_niosv_g_0_hart.sv(274): object "core_ci_f7" assigned a value but never read
Info (12128): Elaborating entity "niosv_g_core_nios_system_intel_niosv_g_0_hart" for hierarchy "nios_system:NiosII|nios_system_intel_niosv_g_0:intel_niosv_g_0|nios_system_intel_niosv_g_0_hart:hart|niosv_g_core_nios_system_intel_niosv_g_0_hart:core_inst"
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(303): object "rd_reg_c" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(314): object "wr_fpr_en" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(315): object "wr_fpr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(316): object "wr_fpr_data" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(327): object "W_instr_valid" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(334): object "M0_nxt_seq_pc" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(356): object "W_instr_word" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(464): object "M0_mem_op" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(470): object "E_jmp" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(471): object "E_ebreak_instr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(472): object "E_ecall_instr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(534): object "D_rs3_fpr_val" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(538): object "E_rs1_fpr_val" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(542): object "M0_rs1_gpr_val" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(548): object "M0_multicycle_instr_done" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(618): object "I_expn_type" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(623): object "W_expn_type" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(764): object "M0_instr_incorrect" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(767): object "M0_itag_incorrect" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(796): object "M0_ecc_rs1" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(797): object "M0_ecc_rs2" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(800): object "ecc_src" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1049): object "I_ebreak_instr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1050): object "I_ecall_instr" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(812): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1236): truncated value with size 4 to match size of target (2)
Warning (10763): Verilog HDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1698): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10270): Verilog HDL Case Statement warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1698): incomplete case statement has no default case item
Warning (10763): Verilog HDL warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1711): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness
Warning (10270): Verilog HDL Case Statement warning at niosv_g_core_nios_system_intel_niosv_g_0_hart.sv(1711): incomplete case statement has no default case item
Best regards,
Domingo.
Hi Broddo and Kian,
Thank you very much for your messages.
First of all, the problem was fixed with your help. Now, my HelloWorld program is working perfectly in Nios V/g.
Effectively, the error was in the address map of the peripheral regions. The end address of the on-chip memory is 0x0900_1fff, and the start address of the JTAG UART controller is 0x1000_1000. Then, simply picking a Peripheral Region A Size of 512 KB and a Peripheral Region A Base Address such as 0x1000_0000 allows the "Hello World from Nios V/g" message to be shown on a Nios V juart terminal. In this HelloWorld example, I keep the main memory address region at the start of the memory map, and the memory addresses of my peripherals are further down. However, I think the partition suggested by Broddo should be more efficient.
Kian, I use Quartus Prime 23.1 Standard Edition because my board (DE0-Nano) integrates a Cyclone IV FPGA. So, I used a method like this one. The warnings have not disappeared, but the processor Nios V/g is working as expected. Your suggestion implies using Quartus Prime Pro Edition, with which I cannot generate a programming SOF file for the Cyclone IV device.
Best regards,
Domingo.
