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Benitez__Domingo's avatar
Benitez__Domingo
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Why my HelloWorld program is not working in Nios V/g while working perfectly in Nios V/m?

Hi, I migrated a golden system reference design (GSRD) for the Terasic DE0-Nano board that is based on a Nios II/e processor to another GSRD for the same board but based on a Nios V/m processor. A ...
Embedded Applications Layer
Nios Architecture
Nios Cpu
  • Benitez__Domingo's avatar
    Benitez__Domingo
    2 years ago

    Hi Broddo and Kian,

    Thank you very much for your messages.

    First of all, the problem was fixed with your help. Now, my HelloWorld program is working perfectly in Nios V/g.

    Effectively, the error was in the address map of the peripheral regions. The end address of the on-chip memory is 0x0900_1fff, and the start address of the JTAG UART controller is 0x1000_1000. Then, simply picking a Peripheral Region A Size of 512 KB and a Peripheral Region A Base Address such as 0x1000_0000 allows the "Hello World from Nios V/g" message to be shown on a Nios V juart terminal. In this HelloWorld example, I keep the main memory address region at the start of the memory map, and the memory addresses of my peripherals are further down. However, I think the partition suggested by Broddo should be more efficient.

    Kian, I use Quartus Prime 23.1 Standard Edition because my board (DE0-Nano) integrates a Cyclone IV FPGA. So, I used a method like this one. The warnings have not disappeared, but the processor Nios V/g is working as expected. Your suggestion implies using Quartus Prime Pro Edition, with which I cannot generate a programming SOF file for the Cyclone IV device.

    Best regards,
    Domingo.

Broddo's avatar
Broddo
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

One of the big differences between the m and g is that the g includes instruction and data caches. You have to specify a peripheral region that spans the memory addresses for every IP you have connected to the Nios V/g in order to allow direct access to their configuration registers. Everything outside of this goes through the cache which can cause problems. As you have a JTAG UART controller as part of your design, be sure that you have defined a peripheral region that includes the JTAG UART memory. You can do this in Platform Designer under the niosv/g settings.

NOTE 1: The built-in timer and dm_agent are automatically excluded from the cache so you don't need to worry about including these in your peripheral region

NOTE 2: If you use something like the Generic Serial Flash Interface IP which includes both bulk memory and control registers, the control registers would need to be in your peripheral region but the bulk memory should be outside that region

What I do to simplify this is that I manually specify the memory address of each of my peripherals that aren't instruction or data memory. I keep this at the start of my memory map. Everything else is at least 1MB further down the map. Then I can specify a peripheral region at 0x0000 of size 1MB.