Forum Discussion
Occasional ContributorWhy my HelloWorld program is not working in Nios V/g while working perfectly in Nios V/m?
Hi Broddo and Kian,
Thank you very much for your messages.
First of all, the problem was fixed with your help. Now, my HelloWorld program is working perfectly in Nios V/g.
Effectively, the error was in the address map of the peripheral regions. The end address of the on-chip memory is 0x0900_1fff, and the start address of the JTAG UART controller is 0x1000_1000. Then, simply picking a Peripheral Region A Size of 512 KB and a Peripheral Region A Base Address such as 0x1000_0000 allows the "Hello World from Nios V/g" message to be shown on a Nios V juart terminal. In this HelloWorld example, I keep the main memory address region at the start of the memory map, and the memory addresses of my peripherals are further down. However, I think the partition suggested by Broddo should be more efficient.
Kian, I use Quartus Prime 23.1 Standard Edition because my board (DE0-Nano) integrates a Cyclone IV FPGA. So, I used a method like this one. The warnings have not disappeared, but the processor Nios V/g is working as expected. Your suggestion implies using Quartus Prime Pro Edition, with which I cannot generate a programming SOF file for the Cyclone IV device.
Best regards,
Domingo.
Frequent ContributorHi Broddo,
Thanks for sharing your thoughts into this area.
Hi Domingo
I talked to the Nios SME over here on this case, first of all there is no Nios V GHRD (work in progress from engineering), was checking whether we have any readily available.
What Broddo mentioned is correct, as Nios V/g have cache, to use peripheral region
- Locate the address map of all soft IP.
- Pick a start address & end address
- Define the address map as peripheral region.
Those warnings is from internal registers which existed since Nios V/g is release which is weird, we also tried replacing directly from Nios V/m to V/g via the replace button (something like this https://www.intel.com/content/www/us/en/docs/programmable/773196/current/hardware-component-37376.html) and didnt get any of those warnings though. Are you using similar method when you changing from V/m to V/g?
Thanks
Regards
Kian
Occasional ContributorHi Broddo and Kian,
Thank you very much for your messages.
First of all, the problem was fixed with your help. Now, my HelloWorld program is working perfectly in Nios V/g.
Effectively, the error was in the address map of the peripheral regions. The end address of the on-chip memory is 0x0900_1fff, and the start address of the JTAG UART controller is 0x1000_1000. Then, simply picking a Peripheral Region A Size of 512 KB and a Peripheral Region A Base Address such as 0x1000_0000 allows the "Hello World from Nios V/g" message to be shown on a Nios V juart terminal. In this HelloWorld example, I keep the main memory address region at the start of the memory map, and the memory addresses of my peripherals are further down. However, I think the partition suggested by Broddo should be more efficient.
Kian, I use Quartus Prime 23.1 Standard Edition because my board (DE0-Nano) integrates a Cyclone IV FPGA. So, I used a method like this one. The warnings have not disappeared, but the processor Nios V/g is working as expected. Your suggestion implies using Quartus Prime Pro Edition, with which I cannot generate a programming SOF file for the Cyclone IV device.
Best regards,
Domingo.
