Introducing the Altera Community AI Responder — Beta
Altera is introducing the AI Responder, an assistant built into the Altera Community to help provide faster, context-aware guidance for Altera product questions. It uses relevant public Altera documentation and Knowledge Database content, with coverage continuing to expand. The AI Responder may provide source references and can hand off complex or out-of-scope questions to an Altera subject-matter expert. As a beta feature, responses may contain errors or omissions, so please review the sources and verify technical guidance against official Altera documentation before implementation. If the response does not fully address your question, add more context and tag ai_responder to continue the discussion. We welcome your feedback as we improve the Community experience.
Run-time errors using EMIF in Agilex 5 NIOS-V design
Hello, I am using Quartus Prime Pro 26.1.1, with the Agilex 5 development board (AXE5-Eagle). I am trying to run the NIOS-V code from the LPDDR4 memory, using JTAG to download/debug. The reset and exception vectors are set to the On-Chip RAM. I used the sample design provided for that board - AXE5 Eagle mipi_hdmi_mira220 and removed everything related to MIPI and HDMI. Added JTAG Uart IP. The resulting sample design is attached (mipi_hdmi_mira220.zip). In the software/ directory you can also see the FreeRTOS BSP I used. I created a simple FreeRTOS application that just prints some string to stdout. What I am seeing is - the RISC-V processor throws exceptions - one of the following - Misaligned Read Address, Misaligned Write Address or Invalid Instruction. This happens in alt_load_section(). If I execute step-by-step, no exception is thrown. But if I just run the application it fails. Is there something else that need to be added/updated/changed, in order to be able and execute code from LPDDR4 using the EMIF IP? I could not find any existing sample design, using NIOS-V and EMIF, with code execution from EMIF. Thank you, D.
not able to use multiple niosV cores at the same time
when I run ultiple niosV cores at the same time im not able to acess each of them even though i am able to detect them , i am faced with even though detecting gives me and i am unable to use the cores likewise this is my file on platform designer
NIOS II "Verify failed" for on-chip memory 128k
Hello! I'm using a Cyclone 10LP FPGA 10CL055YU484I7G FPGA. I have a 11k size program for NIOS II. I have a large on chip RAM (because I have a larger program which I want to use later) of 128k. Everything compiles and links OK. But when I try to download the program I get a "Verify failed between address 0x20000 and 0x2FFFF". The 128K memory is located 0x20000 to 0x3FFFF If I reduce the RAM to 32K, for example, everything works great!!. The initialize memory content option is turned on for the memory The BOOT RAM starts at 0x00000 If I download a bigger program (117k), I still get the same error. ThanksLPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 Pro
Hello, I have a simple design for Agilex 5, using NIOS V/g and EMIF IP with LPDDR4 memory. I have the NIOS V instruction and data manager ports connected to the EMIF IP. Design compiles Ok. But when I create a BSP, in the linker section, there is not a memory device for the LPDDR4. In this thread, a similar problem seems to be mentioned - issue-with-bsp-creation-for-nios-vm-using-lpddr4-on-agilex-5-quartus-24-1--24-3 Does it mean that Address Span Extender IP must be used in order to have the LPDDR4 show in the linker script section, as an available memory device?
NIOS-V QSYS Warning Properties (associatedClock) have been set on
Hello, I have a really basic setup of a NIOS V system, but get Warnings in QSYS (using Quartus 25.1 Standard) about Properties of associatedClock: System: Warning: Warning: nios_subsystem.intel_niosv_m_0: Properties (associatedClock) have been set on interface reset - in composed mode these are ignored Warning: nios_subsystem.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface instruction_manager - in composed mode these are ignored Warning: nios_subsystem.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface data_manager - in composed mode these are ignored Questions: What is "composed mode" and how can I control it? There is no NIOS Parameter associated with it This appears in a basic setup simply by adding NIOS V to the system. How do I get rid of this warning? best regards Fabianlicensing.altera.com never worked
Hi Altera, I need to apply Nios V free license, https://licensing.intel.com went to https://www.altera.com/SSLC , I signed in successfully, however the FPGA Self Service Licensing Center.never worked, I got the error "You do not currently have access to this site." for few weeks, see picture below. Please help fix this issue. Thanks.
