Stratix 10 HPS 8GB SODIMM shared memory for HPS and FPGA
We have custom board with stratix 10 FPGA. the HPS boots from 8GB eMMC and teh linux runs of 2GB soldered DDR4. We also have a 8GB DDR4 SODIMM which we plan to use as a shared memory between the HPS and FPGA. We need help in interfacing this memory with the HPS and FPGA. There are about 8 FPGA modules that need to access the SODIMM along with teh HPS. So total of 8 ports to the memory controller. Can you suggest a solution for this. Is there any muti port wrapper ip for the EMI IP which we can use for this. Also, can the HPS h2f bridge access 8GB memory?
Unable to receive OUT packet on USB in device mode
Hello, I am trying to use USB on Cyclone V soc with tinyUSB. I am able to receive SETUP transaction and send device descriptor, but then I cannot receive and acknowledge the next OUT transaction. I see that DOEPINT0.nakintrpt goes to 1, confirming that the device responds NAK to the OUT transaction, but I don't understand why. Here are the settings that are relevant to me : GAHBCFG.dmaen = 0 DCTL.sgoutnak = 1 GRXFSIZ.rxfdep = 0x50 DOEPMSK.xfercomplmsk = 1 GINTMSK.rxflvlmsk = 1 Written before waiting for OUT packet: DOEPCTL0.epena = 1 DOEPCTL0.cnak = 1 DOEPTSIZ0.xfersize = 0 DOEPTSIZ0.pktcnt = 1 I am lacking ideas of where to search or what could cause this behaviour. Is there anything to take care ? Best regards, Romain
TSE -> SGDMA -> SOC(through f2sdram)
Hi, I'm trying to transfer an old design with multiple TSEs / SGMDAs and a NIOS to a newer Agilex 5. We are also evaluating the use of the SOC instead of the NIOS in the design. I've made a minimized platform design for it but it fails during synthesis with the notorious error for the f2sdram bus: There is both a 'memory -> streaming' and 'streaming -> memory' sgdma in the design present, so both read and write port on the axi bus should be present. If I connect the SGDMA's to the fpga2hps bus the same error is generated. Are there settings in the SGDMAs that needs to be set to a certain value so that the correct read/write avalon MM/AXI interface is generated?
Agilex 5/3 FreeRTOS Heterogeneous SMP SDK Release
Stable Version: v26.1 Quartus Version: 26.1 Supported devices: Agilex™ 3 and Agilex™ 5 Source: https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v26.1-HSMP Release Date: June 24, 2026 Hello Everyone, A new version of the FreeRTOS SDK for Agilex 5/3 is now available. Apart from other fixes and features, the FreeRTOS port now supports heterogeneous SMP for Agilex™ 5 devices. Visit the GitHub repository for instructions on how to get started. Features and Comments Feature Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP Supported Features Limitations / Known Issues A55 boot Yes Yes Yes Yes Single-core boot, Dual-core SMP, Quad-core SMP (Agilex 5) A76 boot NA Yes NA Yes Single-core boot, Dual-core SMP, Quad-core SMP QSPI boot Yes Yes Yes Yes eMMC boot Yes Yes Yes Yes SD boot Yes Yes Yes Yes NAND boot No No No No Clock Manager Yes Yes Yes Yes API to get clock speed of different blocks Reset Manager Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User-defined and free-running modes UART driver Yes Yes Yes Yes Full-duplex TX and RX DMA not supported (planned for future release) I2C driver Yes Yes Yes Yes Master/Slave mode, standard and fast modes QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase I3C driver Yes Yes Yes Yes Master mode, I3C and legacy I2C devices IBI not supported (planned for future release) SPI driver Yes Yes Yes Yes Master/Slave mode write and read NAND driver No No No No SDM Mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes Standard and HS speeds, SDMMC and eMMC devices, FATFS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP, DHCP, IPv4 and IPv6 USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT Yes NT Yes USB mass storage operation WDT driver Yes Yes Yes Yes Interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver Yes Yes Yes Yes Enable/Disable bridges Reboot Manager Yes Yes Yes Yes Warm/Cold reboot FPGA Manager Yes Yes Yes Yes FPGA configuration Legend: Yes: Feature available and tested No: Feature not available in SDK NA: Not applicable NT: Not tested Note: If you find any issues, please raise an issue on the GitHub repository. For more support and assistance, visit our website.
Support Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGA
Hi Altera Support Team, Greetings from Logic Fruit Technologies. This is Bhanu Pratap and I am working on the project in which we are using Agilex-7 SOC FPGA. Goal: Utilize Agiliex-HPS's capability on a Linux OS to control dynamic features of IP Cores at runtime. Problem Statement: We are facing an issue detecting SignalTap with SoC-based designs for runtime debugging while it's enabled and added from the Quartus project to generate the programming file. Brief Description: We are using Quartus 2025.1.1 and Altera's Agilex-7 Devkit(DKSIAAGI027FA: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit -> 4x F-Tile, Rev C). We downloaded the base GHRD design from Altera's GitHub webpage for the corresponding Quartus version. We are following each step to test GHRD and build generation for the Linux OS. We are using HPS First booting mode, we generated the build without modification and tested it. It's working fine according to the GSRD user guide. We have added a custom AXI4 Slave based CSR module to the HSP Lightweight bus to test basic register read/write using Platform Designer. We regenerated the build and re-tested but we are not getting the expected results so we added SignalTap for debugging. Build is generated using the STP file, programmed, and the OS is booting but it's not detecting SignalTap. This looks more like a process gap. We seek your support to fix this issue. Note: If we use an FPGA design without HPS, we are able to add and detect SignalTap. Seeking for urgent support. Thanks Bhanu Pratap
Agilex 5/3 FreeRTOS SMP Support
Stable Version: v25.4 Quartus Version: 25.4 Supported devices: Agilex™ 3 and Agilex™ 5 Source : https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v25.4-SMP Release Date: March 30, 2026 Hello Everyone, FreeRTOS port for A55/A76 HPS now supports SMP. visit the GitHub page for instructions on how to get started. Features and comments Features Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP (A55 x 2 or A76 x 2) Supported features Limitations/ Known issues A55 boot Yes Yes Yes Yes Single core boot, Dual core SMP A76 boot NA Yes NA Yes Single core boot, Dual core SMP QSPI boot Yes Yes Yes Yes SD boot Yes Yes Yes Yes eMMC boot Yes Yes Yes Yes NAND boot No No No No Clk mngr driver Yes Yes Yes Yes API to get clock speed of different blocks Reset mngr driver Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory to memory transfer Only support memory to memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User defined and free running modes UART driver Yes Yes Yes Yes Full duplex Tx and Rx DMA not supported (Planned for future release I2C driver Yes Yes Yes Yes Master mode write and read Standard and fast modes DMA not supported (Planned for future release I3C driver Yes Yes Yes Yes Master mode write and read i3c and legacy i2c devices IBI not supported (Planned for future release) SPI driver Yes Yes Yes Yes Master mode write and read DMA is not supported QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase NAND driver No No No No SDM mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU enable support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes standard and HS speeds SDMMC and eMMC devices Fat FS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP and DHCP IPv4 and IPv6 support USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT Yes NT Yes USB mass storage operation WDT diver Yes Yes Yes Yes interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver NT Yes NT Yes Enable, Disable Reboot mngr Yes Yes Yes Yes Warm/Cold reboot FPGA manager Yes Yes Yes Yes FPGA configuration Yes: Feature available and tested, No: Feature not available in SDK, NA : Not applicable , NT: Not tested Note: If you find any issues, please raise an issue in the GitHub page. For more support/assistance visit our website .
Quartus Error When No Read Path Exists on F2H Bridge
Hello, I am currently investigating a Quartus compilation error related to the FPGA-to-HPS (F2H) bridge on Agilex 5 devices. [Environment] Device: Agilex 5 Tool: Quartus Prime Pro v25.3 [Issue / Observed Behavior] Connection configuration: mSGDMA (Streaming to MM) -> CCT -> F2H bridge (see attached diagram) HDL generation in Platform Designer completes successfully In the RTL Viewer, the F2H-related logic appears to be instantiated, and the F2SOC_RDATA signal seems to be present in the generated RTL However, during Quartus Prime compilation (Synthesis phase), the following errors occur: [Workarounds / Configuration Changes Tested] To ensure that a Read path toward the F2H bridge exists, we tested the following changes: Connecting the F2H bridge via a JTAG Avalon Master Bridge Changing the mSGDMA DMA mode from "Streaming to MM" to "MM to MM", and connecting mm_read to the CCT Enabling mSGDMA Pre-Fetching Options, and connecting descriptor_read_master / descriptor_write_master to the CCT These changes allow a read-capable master to exist toward the F2H bridge. [Question / Confirmation Point] In a configuration where no read-capable master exists toward the F2H bridge, is it expected (by specification) that Quartus determines the F2H interface as not connected, even if the corresponding signals (e.g. F2SOC_RDATA) appear to exist in the RTL? Even if the design logically requires write-only accesses, is a valid read path master still mandatory for the fpga2hps interface to be considered legally connected? Thank you in advance for any clarification.
