Agilex 5E ES Memory Performance Issues
Setup We observed significant performance issues during sequential memory reads in HPS. Target device is A5ED065BB32AE6SR0 from the premium dev kit using the GSRD Example. Sysbench was used to benchmark the memory performance. Test Results For comparison, we also performed the test on an STM32 system (Arm Dual Cortex-A7 800 MHz) and the host PC (Ryzen 7 CPU). Agilex 5E ES STM32MP157F Host PC, Ryzen 7 T0 (sequential read) 480 MiB/s 290 MB/s 78972 MiB/s T1 (sequential write) 4058 MiB/s 190 MB/s 44749 MiB/s T2 (random read) 67 MiB/s 373 MB/s 3461 MiB/s T3 (random write) 52 MiB/s 372 MB/s 3608 MiB/s The test cases where executed as follows: T0: sysbench --num-threads=1 --time=10 memory --memory-block-size=4MiB --memory-total-size=64GiB --memory-access-mode="seq" --memory-hugetlb=off --memory-oper=read run T1: sysbench --num-threads=1 --time=10 memory --memory-block-size=4MiB --memory-total-size=64GiB --memory-access-mode="seq" --memory-hugetlb=off --memory-oper=write run T2: sysbench --num-threads=1 --time=10 memory --memory-block-size=4MiB --memory-total-size=64GiB --memory-access-mode="rnd" --memory-hugetlb=off --memory-oper=read run T3: sysbench --num-threads=1 --time=10 memory --memory-block-size=4MiB --memory-total-size=64GiB --memory-access-mode="rnd" --memory-hugetlb=off --memory-oper=write run Observations The sequential read operation on the Agilex 5 is significantly (factor 10!) slower than the write operation. Especially when comparing to other systems where the sequential read achieves about a third more throughput. Sequential Read vs. Write: The sequential read operation on Agilex 5E ES is about 10x slower than the sequential write operation. On other systems, sequential read typically achieves about 30% higher throughput than write. We found 2 possible issues with the ES devices in the Errata: Degraded HPS EMIF performance with 2MB L3 Cache: https://docs.altera.com/r/docs/825514/current/agilextm-5-es-device-errata-and-user-guidelines/degraded-hps-emif-performance-with-2mb-l3-cache HPS EMIF read throughput less than target: https://docs.altera.com/r/docs/825514/current/agilextm-5-es-device-errata-and-user-guidelines/hps-emif-read-throughput-less-than-target The workaround for 1. is to change the L3-cache to a value different to 2MB. However, this did not improve the performance any way. For the second errata entry, there is no workaround. Question Is the "HPS EMIF read throughput less than target" errata entry the primary cause of the degraded sequential read performance? If confirmed, is this issue resolved in the series Agilex 5 Devices, and what performance improvements can we expect?
Agilex 5/3 FreeRTOS SDK
Stable Version: v25.4 Quartus Version: 25.3 Supported devices: Agilex™ 3 and Agilex™ 5 Source : https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v25.4 Release Date: January 16, 2026 Hello Everyone, FreeRTOS port for A55/A76 HPS in Agilex 5/3 devices are now available for public. visit the GitHub page for instructions on how to get started. Features and comments Yes: Feature available and tested, No: Feature not available in SDK, NA : Not applicable , NT: Not tested Feature Agilex3 Agilex5 Supported features Limitations/ Known issues A55 boot Yes Yes Single core boot SMP not supported A76 boot NA Yes Single core boot SMP not supported QSPI boot Yes Yes SD boot Yes Yes eMMC boot Yes Yes NAND boot No No Clk mngr driver Yes Yes API to get clock speed of different blocks Reset mngr driver Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Memory to memory transfer Only support memory to memory GPIO driver Yes Yes Write, read and interrupt support Timer driver yes yes User defined and free running modes UART driver yes yes Full duplex Tx and Rx DMA not supported I2C driver Yes Yes Master mode write and read Standard and fast modes DMA not supported I3C driver Yes Yes Master mode write and read i3c and legacy i2c devices IBI not supported SPI driver Yes Yes Master mode write and read DMA is not supported QSPI driver Yes Yes QSPI flash read/write/erase NAND driver No No SDM mailbox driver Yes Yes SDM commands with SIP_SVC SMMU enable support Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes standard and HS speeds SDMMC and eMMC devices Fat FS support Ethernet stack Yes Yes TCP/IP, UDP, ICMP and DHCP IPv4 and IPv6 support 100mbps and 1gbps operation USB 2.0 stack NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT yes USB mass storage operation WDT driver Yes Yes interrupt or reset on timer expiry EDAC support Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Error injection and detection Bridge driver NT Yes Enable, Disable Reboot mngr Yes Yes Warm/Cold reboot FPGA manager Yes Yes FPGA configuration Note: If you find any issues, please raise an issue in the GitHub page. For more support/assistance visit our website .