F2SDRAM test inquiries.
Hi Guys, I am testing the F2SDRAM bridge. 32 bit address, 256bits data. Due to recurring missing Verilog file errors for the Qsys adapter IP whenever switching PCs, I removed the adapter earlier and am currently testing by directly exporting f2s from the HPS to the top level. I implemented tester logic on the FPGA side to write and read 256-bit data once per transaction (len=0) for 2048 comparisons, but the B channel signal keeps returning 2'b11 (DECERR). I implemented the tester logic on the FPGA side to perform 2,048 read/write comparison cycles with 256-bit data in single-beat transactions (len=0) using a base address of 0x8000_0000. However, I am at a loss because the B channel signal continuously returns 2'b11 (DECERR). Debugging this solely based on the B channel response is quite challenging. For reference, I am currently running this test on an 013b devkit using the GHRD Linux Reference Design, triggering the start signal via Signal Probe after the kernel has fully booted up Could this be an issue with sideband signals or the kernel driver? Gemini suggests that the bridge might be in reset or it could be due to SMMU. I have already disabled SMMU. As expected, learning and applying new technology is always tough. Thank.
Agilex 5E HPS and Linux
Hi. 1. Is there a simple method to run two Linux systems on HPS, i.e.: Linux 1 - 2xA55 and Linux 2 - 2xA76 with different sets of peripherals? 2. Is it possible to use one Ethernet port by these two Linux systems. 3. Is there a simple method for communication between these two Linux systems?
F2SDRAM fails to synthesize with custom logic
Hello guys, We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-level ports. Does anyone know why this is happening? Also, is there an example design for F2SDRAM available? The GHRD is not very helpful since it only includes the JTAG master. I suspect it might be a design issue, so I even removed the adapter and connected it only within Qsys, but it’s still acting up like this. Does anyone know why this is happening even though everything is clearly declared and connected? HudsonAgilex 5/3 FreeRTOS Heterogeneous SMP SDK Release
Stable Version: v26.1 Quartus Version: 26.1 Supported devices: Agilex™ 3 and Agilex™ 5 Source: https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v26.1-HSMP Release Date: June 24, 2026 Hello Everyone, A new version of the FreeRTOS SDK for Agilex 5/3 is now available. Apart from other fixes and features, the FreeRTOS port now supports heterogeneous SMP for Agilex™ 5 devices. Visit the GitHub repository for instructions on how to get started. Features and Comments Feature Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP Supported Features Limitations / Known Issues A55 boot Yes Yes Yes Yes Single-core boot, Dual-core SMP, Quad-core SMP (Agilex 5) A76 boot NA Yes NA Yes Single-core boot, Dual-core SMP, Quad-core SMP QSPI boot Yes Yes Yes Yes eMMC boot Yes Yes Yes Yes SD boot Yes Yes Yes Yes NAND boot No No No No Clock Manager Yes Yes Yes Yes API to get clock speed of different blocks Reset Manager Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User-defined and free-running modes UART driver Yes Yes Yes Yes Full-duplex TX and RX DMA not supported (planned for future release) I2C driver Yes Yes Yes Yes Master/Slave mode, standard and fast modes QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase I3C driver Yes Yes Yes Yes Master mode, I3C and legacy I2C devices IBI not supported (planned for future release) SPI driver Yes Yes Yes Yes Master/Slave mode write and read NAND driver No No No No SDM Mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes Standard and HS speeds, SDMMC and eMMC devices, FATFS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP, DHCP, IPv4 and IPv6 USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT Yes NT Yes USB mass storage operation WDT driver Yes Yes Yes Yes Interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver Yes Yes Yes Yes Enable/Disable bridges Reboot Manager Yes Yes Yes Yes Warm/Cold reboot FPGA Manager Yes Yes Yes Yes FPGA configuration Legend: Yes: Feature available and tested No: Feature not available in SDK NA: Not applicable NT: Not tested Note: If you find any issues, please raise an issue on the GitHub repository. For more support and assistance, visit our website.Stratix 10 Linux SD card booting
Hi Altera Community, I tried multiple attempts to boot the SD card from Rocketboard.org. https://releases.rocketboards.org/ I downloaded and booted the SD card with the .wic image file. It only has the .itb file by default in the boot partition. Whenever I try to boot, it asks for the U-Boot.img file. And also it says "failed to load "socfpga_stratix10_socdk.dtb" even if the file is there. And then I compiled my simple HPS design and can easily program the FPGA from the Quartus Programmer (rbf and sof file), but whenever I try to overlay it, like say: echo overlay.dtb > /sys/kernel?config?device-tree/overlays/0/path It says "FPGA manager error, timeout," and so on. Does any community member have notes or steps that you made to boot the SD card of the Stratix 10 FPGA? I am following this link: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderStratix10
Unstable fpga programming using HPS(Agilex3)
Hi I have a problem where the fpga programming sometime fail when using the overlay method described here under "Reconfiguring Core Fabric from Linux": https://altera-fpga.github.io/rel-25.3.1/embedded-designs/agilex-3/c-series/boot-examples/ug-linux-boot-agx3/#reconfiguring-core-fabric-from-u-boot Here I have first two successful attempt then it fail on the third: root@agilex3:~# rmdir /sys/kernel/config/device-tree/overlays/0 ; sleep 1 ; mkdir /sys/kernel/config/device-tree/overlays/0 ; cd /lib/firmware/ ; sleep 1; echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path rmdir: '/sys/kernel/config/device-tree/overlays/0': No such file or directory [ 182.671913] fpga_manager fpga0: writing overlay.rbf to Stratix10 SOC FPGA Manager [ 184.865664] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/firmware-name [ 184.876007] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/config-complete-timeout-us root@agilex3:/lib/firmware# rmdir /sys/kernel/config/device-tree/overlays/0 ; sleep 1 ; mkdir /sys/kernel/config/device-tree/overlays/0 ; cd /lib/firmware/ ; sleep 1; echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path [ 196.530735] fpga_manager fpga0: writing overlay.rbf to Stratix10 SOC FPGA Manager [ 198.659279] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/firmware-name [ 198.669650] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/config-complete-timeout-us root@agilex3:/lib/firmware# rmdir /sys/kernel/config/device-tree/overlays/0 ; sleep 1 ; mkdir /sys/kernel/config/device-tree/overlays/0 ; cd /lib/firmware/ ; sleep 1; echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path [ 214.383163] fpga_manager fpga0: writing overlay.rbf to Stratix10 SOC FPGA Manager [ 217.508857] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x00004405 [hwprod 0x00004408, hwcons 0x00004405] [ 217.509907] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x00004407 [hwprod 0x00004408, hwcons 0x00004405] U-Boot SPL 2025.10 (May 18 2026 - 08:34:29 +0000) Reset state: Cold MPU 800000 kHz L4 Main 400000 kHz L4 sys free 100000 kHz L4 MP 200000 kHz L4 SP 100000 kHz SDMMC 200000 kHz init_mem_cal: Initial DDR calibration IO96B_0 succeed DDR: Calibration success is_mailbox_spec_compatible: IOSSM mailbox version: 1 LPDDR4: 1792 MiB ecc_interrupt_status: ECC error number detected on IO96B_0: 0 SDRAM-ECC: Initialized success Does anybody know how to debug and fix this? I'm using Quartus Prime Version 25.3.0 Build 109 Devboard: DK-A3W135BM16AEA: Agilex™ 3 FPGA and SoC C-Series Development Kit
