Power management Agiilex 3/5 - Powerdown then HPS restart ?
I read in the power management section of (841346) Section 9 "Only power-off operations are supported, and they are done one time as a static option through boot mode user configuration. After power is turned off, the power manager does not support powering back on the CPU cores or L3 cache blocks." As I understand it = for a(partial ) power down , or power up of the HPS, the system needs to set some memory locations and then trigger a HPS restart and ther SDM has control then passes it to the FSBL. , then the FSBL can look at these locations and see what power mode it needs to come up or down as the system requires...... IE to change the power settings, there needs to be an HPS restart , or complete device configuration reload ? Perhaps put another way : In HPS boot-first mode : When a power CHANGE is required in the HPS domain, can the fabric stay running (assuming that there are no outstanding HPS<> fabric DMA requests or transactions pending across the fabric<>HPS bridge ) ? regards, glen.Agilex 5/3 FreeRTOS SDK Release
Stable Version: v26.1.1 Quartus Version: 26.1.1 Supported devices: Agilex™ 3 and Agilex™ 5 Source: https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v26.1.1 Release Date: October 9, 2026 Hello Everyone, A new version of the FreeRTOS SDK for Agilex 5/3 is now available. This release contains some fixes, along with UHS-1(SDR12/25/50) support for SD/eMMC. Visit the GitHub repository for instructions on how to get started. Features and Comments Feature Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP Supported Features Limitations / Known Issues A55 boot Yes Yes Yes Yes Single-core boot, Dual-core SMP, Quad-core SMP (Agilex 5) A76 boot NA Yes NA Yes Single-core boot, Dual-core SMP, Quad-core SMP QSPI boot Yes Yes Yes Yes eMMC boot NT Yes NT Yes SD boot NT Yes NT Yes NAND boot No No No No Clock Manager Yes Yes Yes Yes API to get clock speed of different blocks Reset Manager Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User-defined and free-running modes UART driver Yes Yes Yes Yes Full-duplex TX and RX I2C driver NT Yes NT Yes Master/Slave mode, standard and fast modes QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase I3C driver NT Yes NT Yes Master mode, I3C and legacy I2C devices SPI driver NT Yes NT Yes Master/Slave mode write and read NAND driver No No No No SDM Mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes Standard and HS HS, and UHS-I (SDR12/25/50) speeds, SDMMC and eMMC devices, FATFS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP, DHCP, IPv4 and IPv6 USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack Yes Yes Yes Yes USB mass storage operation WDT driver Yes Yes Yes Yes Interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver Yes Yes Yes Yes Enable/Disable bridges Reboot Manager Yes Yes Yes Yes Warm/Cold reboot FPGA Manager Yes Yes Yes Yes FPGA configuration Legend: Yes: Feature available and tested No: Feature not available in SDK NA: Not applicable NT: Not tested Note: If you find any issues, please raise an issue on the GitHub repository.
Introducing the Altera Community AI Responder — Beta
Altera is introducing the AI Responder, an assistant built into the Altera Community to help provide faster, context-aware guidance for Altera product questions. It uses relevant public Altera documentation and Knowledge Database content, with coverage continuing to expand. The AI Responder may provide source references and can hand off complex or out-of-scope questions to an Altera subject-matter expert. As a beta feature, responses may contain errors or omissions, so please review the sources and verify technical guidance against official Altera documentation before implementation. If the response does not fully address your question, add more context and tag ai_responder to continue the discussion. We welcome your feedback as we improve the Community experience.Store custom keys on SDM Agilex3
Hi I know it's possible to store encryption and siging keys on the SDM for fpga firmware decryption and authentication, but is it possible to store my own keys on it? I will use the key to decrypt my own software files on the HPS, so I need some way to send the ecrypted software to the SDM then the SDM will use the key to decrypt it and send it back. Is there any documentation or tutorial for this?
Release 26.1.1
Version: Release 26.1.1 PRO Quartus Build/TAG: B130/QPDS26.1.1_REL_GSRD_PR Release Date: August 17, 2026 Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7, Startix® 10 Release Type: Major release/Binary release Binary Release Path: http://releases.rocketboards.org/2026.08/ Release Page: https://github.com/altera-fpga/gsrd-socfpga/releases/tag/QPDS26.1.1_REL_GSRD_PR Major Features Released Agilex™ 5 XEN Hypervisor 5 System Example Design https://altera-fpga.github.io/rel-26.1.1/virtualization/hypervisors/xen/ug-xen-agx5e-premium-065b/ , https://altera-fpga.github.io/rel-26.1.1/virtualization/hypervisors/xen/ug-xen-agx5e-premium-065a/ Agilex™ 5 RYO OPTE System Example Design Agilex™ 5 Quartus Reference Design using VDS Agilex™ 3 Time-Sensitive Networking (TSN): PHY configuration 2 (RGMII from FPGA HVIO) System Example Design Agilex™ 5 Performance Optimized Baseline SED support Agilex™ 5 DataMover / Bridge and Memory Benchmark System Example Design https://altera-fpga.github.io/rel-26.1.1/embedded-designs/agilex-5/e-series/premium-065a/data-mover/ug-data-mover-agx5e-premium-065a/ Agilex™ 3 support of FreeRTOS Agilex™ 5 Terasic DE25-Nano Board System Example DesignHow to Generate Altera HAL for HPS?
Hi, I am using Quartus 26.1 with the Agilex 5 Modular Development Kit (Device number: A5ED065BB32AE6SR0) and I have a few questions about BSP Generation for Hard Processor System (HPS). For reference I am following the Quartus Prime Pro Edition Version 26.1 User Guide. 1. How do I generate Altera HAL for HPS? When I use the BSP Editor in platform designer, I can only generate the system.h file that only has macros for EMIF, even though other peripherals are also connected to the HPS. How do I generate macros for the H2F bridges and HAL API Files for the HPS? 2. How do I input a SOPCINFO file into the BSP Editor? The Quartus Prime Pro Edition User Guide shows that I should be able to input SOPCINFO file as the system file (see above image) but Quartus only gives me the options of QSYS and IP file (see below image). Thank you for the help!Agilex3 ip fragmented packets gets corrupted
Hi I have a problem where the agilex3 HPS is not able to correctly reassemble ip-fragmented packets, I have included two pcaps one that show what the host is sending to the agilex and one that show the reception on the agilex. As you can see in the agilex.pcapng some of the packets gets corrupted in strange ways and gets wrong checksum. I use the DK-A3W135BM16AEA: Agilex® 3 FPGA and SoC C-Series Development Kit and has based my project on this example: https://altera-fpga.github.io/rel-25.3.1/embedded-designs/agilex-3/c-series/gsrd/ug-gsrd-agx3/ Anybody know whats going on here?
Agilex 3 Baremetal example
We need to be able to run the Agilex 3 as baremetal We tried to re-target this Agilx5 baremetal tutorial: Baremetal Hello World Example for Agilex™ 5 Premium To be used on Altera's Agilex 3 EVB : GitHub - altera-fpga/agilex3c-ed-gsrd: Altera Agilex 3 C-series GSRD · GitHub but this seems to be too great of a task for us - everything there is custom made for the Agilex 5 Please help.
F2SDRAM test inquiries.
Hi Guys, I am testing the F2SDRAM bridge. 32 bit address, 256bits data. Due to recurring missing Verilog file errors for the Qsys adapter IP whenever switching PCs, I removed the adapter earlier and am currently testing by directly exporting f2s from the HPS to the top level. I implemented tester logic on the FPGA side to write and read 256-bit data once per transaction (len=0) for 2048 comparisons, but the B channel signal keeps returning 2'b11 (DECERR). I implemented the tester logic on the FPGA side to perform 2,048 read/write comparison cycles with 256-bit data in single-beat transactions (len=0) using a base address of 0x8000_0000. However, I am at a loss because the B channel signal continuously returns 2'b11 (DECERR). Debugging this solely based on the B channel response is quite challenging. For reference, I am currently running this test on an 013b devkit using the GHRD Linux Reference Design, triggering the start signal via Signal Probe after the kernel has fully booted up Could this be an issue with sideband signals or the kernel driver? Gemini suggests that the bridge might be in reset or it could be due to SMMU. I have already disabled SMMU. As expected, learning and applying new technology is always tough. Thank.
