Why does the Power Thermal Analyzer tool display device family compatibility errors when opening files from different device families in Quartus® Prime Pro Edition Software version 25.3?
Description Due to a problem in Quartus® Prime Pro Edition Software version 25.3, during a single session, if a new Power Thermal Analyzer (PTA) design file is created targeting a specific device family, all subsequent PTA design files opened will be loaded targeting the same device family. This occurs regardless of the actual target device defined in those files. This problem occurs when switching between Stratix® 10 FPGA and Agilex® FPGA device families within the same session. For example, if you first create a PTA file for a Stratix™ 10 FPGA device and then open a PTA file meant for an Agilex® 7 FPGA device, the Agilex® 7 FPGA file will incorrectly be loaded as targeting the Stratix® 10 FPGA device. This results in the error: "Error (25383): The Stratix® 10 FPGA PTA does not currently support opening files created by the Agilex® 7 FPGA PTA. Import canceled." The same issue occurs in reverse when opening Stratix® 10 FPGA PTA files after creating an Agilex® FPGA PTA file. Resolution You can avoid this issue using one of the following methods: Close and reopen Quartus® Prime Pro Edition Software before opening PTA files from different device families. This method works when PTA is launched from Quartus® Prime Pro Edition Software; for standalone PTA, closing and reopening PTA before opening different device family files is more appropriate. Create a new PTA file using the target device family, then open the desired file from the recently created PTA file. Use the open_design_file Tcl command by copying the equivalent Tcl command displayed in the Tcl Console and modifying it to replace the target device family in the -family parameter to match the desired device family. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why is there a random hexadecimal number in my TCL console?
Description Due to a problem in the Quartus® Prime Pro Edition Software, you may see a random hexadecimal number printed in the TCL console after running the set_instance_assignment command. Resolution It is safe to ignore this number. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.
Why do I get the error Internal Error "No Active Family" when trying to generate a programming JAM file via command line "quartus_pfg"
Description When trying to generate a JAM programing file (.jam) via the quartus_pfg command line from a Chain Description File (.cdf). quartus_pfg -c <file>.cdf <file>.jam You may get the following error message: Internal Error: Sub-system: PGMIO, File: /quartus/pgm/pgmio/pgmio_jam.cpp, Line: 2873 No Active Family Stack Trace: Quartus 0x3cce3e: PGMIO_JAM::jam2_filter(int, PGMIO_JTAG_UNI_ENGINE*, std::basic_ifstream >&, std::ostream&) + 0x582 (pgm_pgmio) Quartus 0x3d0a7a: PGMIO_JAM::jam2_create_file(int, PGMIO_JTAG_UNI_ENGINE*) + 0x846 (pgm_pgmio) Quartus 0x3d4ec2: PGMIO_JAM::create_output_file(std::vector >*, FIO_PATH const&, bool) + 0x3e8c (pgm_pgmio) This error may be due to an issue were the source programming files on the .cdf file not being valid. Resolution To work around this problem, verify your programing source file or files with the following command line: quartus_pfg -i <source>.sof This command will help you determine if your source file or files are valid and invalid and provide additional info on the issues with the invalid files for troubleshooting. Replace the invalid files with valid ones once identified. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why are there unexpected timing paths with HPS EMAC clocks in the timing report when HPS EMAC is routed to the FPGA?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and earlier, you may see unexpected timing paths in the timing report for EMAC clocks when HPS EMAC is routed to the FPGA. Resolution The top entity below helps to understand the EMAC clocks, "emac1_gtx_clk" and "user0_clock_clk" used in the design, where EMAC1 is routed to the FPGA: To work around this problem, use the following SDC constraints: set_false_path -fall_from emac1_gtx_clk -rise_to emac1_gtx_clk set_false_path -fall_from emac1_gtx_clk -rise_to user0_clock_clk Additional Information The problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the F-Tile Triple-Speed Ethernet IP with core variation 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile) drop packets?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1, you may see packets dropped when the F-Tile Triple-Speed Ethernet IP is configured to 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile) variant. This is because the IP default settings for flux_mode are set as "FLUX_MODE_FLUX_MODE_SNIFFER" and rx_adaptation_mode is set as "RX_ADAPTATION_MODE_FLUX_ADAPTATION". Since the F-Tile Triple-Speed Ethernet IP line rate is 1.25 Gbps, the recommended flux_mode needs to be set as "FLUX_MODE_FLUX_MODE_BYPASS" and rx_adaptation_mode needs to be set as "RX_ADAPTATION_MODE_MANUAL_ADAPTATION". Resolution To work around the above problem, you can add the following assignment to the project setting .qsf file: set_instance_assignment -name HSSI_PARAMETER "flux_mode=FLUX_MODE_FLUX_MODE_BYPASS" -to <RX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "rx_adaptation_mode=RX_ADAPTATION_MODE_MANUAL_ADAPTATION" -to <RX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.Why does marginal degradation of 1.8V VIL I/O standard occur on Stratix® 10 FPGAs and Agilex® FPGAs family SDM I/O pins after long-term operation?
Description On all Stratix® 10 FPGA and Agilex® FPGA devices, when the board MSEL is set to JTAG but Quartus® Prime design software is configured to AS or AVST×8, and SDM I/O pins are left unconnected (NC), long-term operation may cause the 1.8V VIL on those SDM I/O pins to degrade below the datasheet specification of 0.5985V (0.35 × 1.71V). Refer to device datasheet under Single-Ended I/O Standards Specifications section for SDM IO I/O standard specification. The degradation can lead to configuration issues. Resolution Select AVST×16 as the configuration scheme in Quartus when using JTAG MSEL with all SDM I/O pins left unconnected. AVST×16 does not use any SDM I/O pins, preventing the degradation. Refer to Configuration User Guide for the steps to enable dual-purpose pins when setting AVSTx16 mode in Quartus. Starting in Quartus® Prime Pro edition software version 26.1, a note will be updated in the Configuration User Guide and the tooltips for the Configuration scheme category under Device and Pin Options in Quartus.Why do I see a simulation failure with the F-Tile Multi Channel DMA IP for PCI Express* Design Example using the Quartus® Prime Pro Edition Software version 26.1 ?
Description Due to a problem in the Quartus Prime Pro Edition Software version 26.1, you may encounter simulation errors with the F-Tile Multi Channel DMA IP for PCI Express* Design Example. Synopsys VCS/VCS-MX: Error-[SE] Syntax error Following verilog source has syntax error : "./../..//pcie_ed_sim_tb.v", 2015: token is ')'... Error-[TMENF-IL] Top Module/Entity not found Top module/entity/config "pcie_ed_sim_tb.pcie_ed_sim_tb" is not found in library "PCIE_ED_SIM_TB". Error-[NM] No modules defined No modules defined in current design file(s). Siemens Questasim: ** Error: /mentor/questasim/2025.3/linux64/linux_x86_64/qrun failed. Error in macro ./run_msim_setup.tcl line 52 Cadence Xcelium: xmelab: *E,NOUNIT: Unable to find a unit named 'pcie_ed_sim_tb.pcie_ed_sim_tb' in the libraries. xmsim: *F,NOSNAP: Snapshot 'pcie_ed_sim_tb.pcie_ed_sim_tb' does not exist in the libraries. Aldec Riviera-Pro: Error: VCP2000 .../pcie_ed_sim_tb/pcie_ed_sim_tb/sim/pcie_ed_sim_tb.v : (1951, 6): Syntax error. Unexpected token: ). This problem is attributed to a limitation in the provided simulation testbench within this software release. It is important to note that this behavior is confined to the simulation environment and does not impact the functionality or performance of the design on hardware. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.Why does the SDI Audio IP not appear in the Quartus® Prime Pro Edition Design Software Versions 25.1 and 25.1.1?
Description Due to a problem in the Quartus® Prime Pro Edition software versions 25.1 and 25.1.1, the SDI Audio IP is not visible in the IP Catalog. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.Is there any known issue when enabling the Open Drain Programmable I/O Element Feature of an Agilex® 7 FPGA M-Series HPS IO using Quartus® Prime Software Suite version 25.1.1?
Description Yes, due to an issue with Quartus® Prime Software Suite version 25.1.1 when enabling the Open Drain Programmable I/O Element Feature of an Agilex® 7 FPGA M-Series HPS IO, this change is not applied correctly to the bitstream. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.Is there any known issue when enabling the Open Drain Programmable I/O Element Feature of an Agilex® 7 FPGA F-Series and I-Series HPS IO using Quartus® Prime Software Suite version 25.1.1?
Description Yes, due to an issue with Quartus® Prime Software Suite version 25.1.1 when enabling the Open Drain Programmable I/O Element Feature of an Agilex® 7 FPGA F-Series and I-Series HPS IO, this change is not applied correctly to the bitstream. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.
