Need PCI Express 5.0 for your next FPGA design? Check out Intel® Agilex™ I-series and M-series FPGAs
Are you designing systems that need PCI Express (PCIe) 5.0 capability? If so, you’ll want to take a good look at the Intel® Agilex™ I- and M-series FPGAs and SoC FPGAs because these programmable-logic devices incorporate PCIe 5.0 capabilities and have just passed PCI-SIG compliance tests.5.3KViews2likes0CommentsUnable to generate AXI Streaming Intel FPGA IP for PCIe Example design for F-Tile FPGA Agilex 7 R24C
Hello Team, I am trying to generate an example design for the AXI Streaming Intel FPGA IP for PCI Express IP. It supports F-Tile PCIe in the design, but when trying to generate the Example design as an Endpoint I am unable to generate one. Is there any Endpoint Example design for the F-Tile, could you please provide me with the link for the same.| Quartus Prime Pro 2024.1 Agilex 7 AGFB014R24C2E2V Thank you, Best RegardsSolved877Views1like7CommentsFPGA writing to SSD
FPGA A (which is part of an existing system) transmits data using Serial Lite at 24 Gb/s. This data shall be received by FPGA B (to be designed) and written to an external storage device (SSD or multiple SSDs). The data volume is in the order of < 10 Terabytes. I thought of 2 possible approaches: 1. Connect the storage devices directly to FPGA B (using a custom board) and have the FPGA write directly to them. (I assume this will require implementing an NVMe controller in FPGA B). 2. Install FPGA B inside a PC like system where it will communicate via PCIe and do DMA transactions towards the storage devices. Which of the above approaches offers better performance ?955Views1like3Comments