Can't find Agilex 7 M I/O PLL Reconfiguration Design Example
Hi, Recently updated document "Agilex™ 7 Clocking and PLL User Guide M-Series", 769001 2025.10.09 refers to a design example which uses an EMIF Calibration IP for I/O PLL reconfiguration: 6.1.7. Design Example for I/O PLL Reconfiguration I can't find this design on Intel or Altera sites. Can anyone please tell if it exists. I can find very similar Agilex 7 PLL reconfig examples but they use different calibration IP, not usable with Agilex 7M devices. I'm trying to utilize IOPLL's dynamic output phase adjustment only. This was easy with earlier generation devices as the I/O PLL provided a specific control interface for this purpose. Phase shift control port or something similar. Thanks, Ju-ti
Error: dut.p0_hip_status has no associated reset.
Hello Altera I am using Quartus Prime Pro 25.1.0 build 129 03/26/2025 SC Pro Edition. In my Agiliex 7 Design project, I have Intel R-Tile MCDMA for PCI Express intel_pcie_rtile_mcdma Version 5.3.1 Ip instantiated as "dut". in parameters settings I have enabled to have hip status interface. https://www.intel.com/content/www/us/en/docs/programmable/683821/25-1-1/hard-ip-status-interface.html this interface is connected to a custom design QCP file. The QCP uses "app_clk" and "app_nreset_status" from dut ip as its clk and reset inputs. They go through clock bridge and reset bridge. Clock and reset outputs from these bridges are used internally in custom logic code. In platform designer as I connect "dut.p0_hip_status" and "custom_module.pcie_ep_hip_status_in" ports, I get an error as following "Error: pcie_ed: Interfaces custom_module.pcie_ep_hip_status_in and dut.p0_hip_status must have matching associated resets, but dut.p0_hip_status has no associated reset." This Error does not make sense to me, as dut`s hip status interface and my qcp`s status interface ports shows correct clock and reset association in component instantiation tab; and my custom design uses same clock and reset to its clock and reset bridge inputs. can you please help me to understand what is this error about and how do i resolve it?
Please let me know how to get a GTS license for Agilex 5.
I have already some licenses, for example, IP-SDI-II, IP-DP, IP-HDMI and so on. I want to use these IP on Agilex 5. However, Ordering Code is not match the IPs I have when I searched the IP User Guide. SDI => IP-GTS-SDI-II Display Port => IP-GTS-DP Is it possible to get a License of IP-GTS-xxx, if I regenerate in my SSLC ? Or, Need I buy the new licenses for GTS Transceiver? Thanks.
ALT PLL GUI MESSDED UP ON INVOCATION
Hi All ALTERA Experts, I have a problem setting up a new PLL due to the GUI looking like the mess you can see in my attached screenshot. I am using Quartus Standard edition Version 25.1 I am on a windows 10 machine and all of the other IP GUIs seem to work fine, its just this PLL IP GUI that seems to get messed up. I am using a MAX10 FPGA. Both my PC and Graphics card are working fine. Can anybody suggest why this occurs ? Thanks, BarryIOPLL output clock issue Stratix10
Hi Team, I configured iopll IP for three output clocks, (outclk0)100MHz, (outclk1)200MHz and (outclk2)600MHz. Ref clock is 100MHz. I see duty cycle variation in the generated clock of 200MHz from iopll. I'm capturing the clocks using signal tap analyzer at a frequncy of 600MHz, genrated by same iopll. Why the duty cycle is varying from 50%? Clock waveform IOPLL Settings
Request for an official email to declare Intel acquired structured eASIC company.
Our company want to send an quotation to eASIC company before, but found that Intel acquired structured ASIC company eASIC into Programmable Systems Group (PSG). Could you please send us an official email to declare this situation for our record, thank you.
