Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Do Intel® MAX® 10 devices have an exposed pad at the bottom of the 144-pin EQFP (E144) package?
Description Yes, Intel® MAX®10 devices in the E144 package have an exposed pad at the bottom of the package. The exposed ground pad is used for electrical connectivity and not for thermal purposes. Therefore, you must connect the exposed ground pad to the ground plane of the PCB. To know the exposed pad dimensions, refer to dimensions D2 and E2 for the E144 package, which can be found on the Package and Thermal Resistance (MAX 10) page. Resolution The documentation has been updated.Error (209014): CONF_DONE failed to go high in device <number>
Description Due to an issue in the Quartus® Prime software version 16.1.1 and earlier, you may observe this error in the Quartus Prime programmer when programming MAX® 10 devices with date code 1625 and onwards, using the following sequence: Full-chip erase --> SOF configuration --> Power cycle/pulse nCONFIG --> SOF/POF programming. Resolution This issue is fixed in Quartus Prime software version 16.1.2.Error (14703): Invalid internal configuration mode for design with pre-initialized eram
Description Due to a known problem in the Quartus® II software version 14.0, you may get this error when compiling a design that targets a MAX® 10 device that supports configuration modes with memory initialization. The design utilizes internal memory blocks. Resolution To work around this problem, use the following Intel® Quartus® II Settings File (.qsf) assignment set_global_assignment -name ENABLE_ERAM_PRELOAD ON This problem was fixed in version 15.0 of Intel® Quartus® software.How do I use the Altera PDN Tool to evaluate decoupling requirements for a MAX 10 device?
Description To evaluate decoupling requirements for a MAX® 10 device you can use the device agnostic version of the Altera® Power Delivery Network (PDN) Tool. To calculate the target impedance of each MAX 10 device supply, you should use the following transient current and voltage ripple percentages: MAX 10 Supply Rail Transient Current Voltage Ripple VCC 50% 5% VCCIO 100% 5% VCCA 10% 5% VCCD_PLL 10% 3% VCCA_ADC 50% 2% VCCINT 50% 3% Setting Ftarget to 70MHz or higher should result in a robust PDN. Related Articles How do I interpret the Recommended Operating Conditions and Allowable Ripple recommendations of Altera devices? Why might the Altera Power Distribution Network (PDN) Tool, Auto Decoupling Mode result in a Zeff that is too high?What are the programmable IOE delay specifications for Intel® MAX® 10 devices with -I6 speed grade?
Description The Intel® MAX® 10 FPGA Device Datasheet currently doesn’t provide the programmable IOE delay specifications for -I6 speed grade. You can find the programmable IOE delay specifications for Intel® MAX® 10 devices with -I6 speed grade in the following table. < Programmable IOE Delay for Intel® MAX® 10 Device -I6 speed grade (Slow Corner) > Parameter Row Column Slow corner (ns) Input delay from pin to internal cells 1.797 1.788 Input delay from pin to input register 2.042 2.02 Delay from output register to output pin 1.049 0.952 The specifications for fast corner are the same as -I7 speed grade. Refer to Programmable IOE Delay for Row Pins and Programmable IOE Delay for Column Pins in the Intel® MAX® 10 FPGA Device Datasheet. Resolution The programmable IOE delay specifications for -I6 speed grade Intel MAX 10 devices will be added in a future release of the Intel® MAX® 10 FPGA Device Datasheet.Why do some I/O pins of Intel® MAX® 10 devices 10M04SAU324I7G and 10M04SCU324C8G stay low rather than tri-state with pull up during normal ISP?
Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 18.0, some I/O pins of Intel® MAX® 10 devices 10M04SAU324I7G and 10M04SCU324C8G will remain low rather than tri-state with pull-up during normal ISP. This is related to a previous known problem, described in Why do I observe some I/O pins being driven to LOW (GND) during the POF file programming for MAX 10 devices? Resolution This problem is fixed in Intel® Quartus® Prime Standard Edition Software version 19.1.For some MAX 10 device designs, the Fitter causes an abnormal exit during the Fitter stage when listen_to_nsleep_signal is set
Description In the Quartus II software version 15.0, a legality check issue in the Fitter causes an abnormal exit during the Fitter stage when the listen_to_nsleep_signal parameter is explicitly set to true but the nsleep port is not connected. This issue applies to designs targeting the MAX 10 ZB16/25/50 device only. The Quartus II software should generate a user error, but causes an abnormal exit instead. You might encounter the abnormal exit if you use an input buffer atom, or Altera's general-purpose I/O (GPIO) Lite to construct your IP. Resolution There is no workaround. This issue will be fixed in a future software release.Why does Intel® Quartus® Prime Programmer fail to program an Intel® MAX® 10 device with JTAG Secure mode enabled in a device chain?
Description You will observe Intel® Quartus® Prime Programmer failure when you have an Intel® MAX® 10 device with JTAG Secure mode enabled in multiple device JTAG chain. Resolution To work around this issue, perform Intel® Quartus® Prime Programmer programming separately between the Intel® MAX® 10 device with JTAG Secure mode enabled and the rest of the devices in the JTAG chain. - When you are programming an Intel® MAX® 10 device with JTAG Secure mode enabled, you need to bypass the rest of the devices in the JTAG chain - When you are programming the rest of the devices in the JTAG chain then you need to bypass the Intel® MAX® 10 devices with JTAG Secure mode enabled. This problem is fixed starting with the Intel® Quartus® Prime Software version 21.1.MGL_INTERNAL_ERROR: Port object altpll_avalon|altpll inst sd1|phasecounterselect of width 3 is being assigned the port altpll_avalon|w_phasectrsel of width 4 which is illegal, as port widths don't match nor are multiples.
Description Due to a problem in the Quartus® II software version 15.0 and earlier, you will get this error if an ALTPLL is generated in the Platform Designer with the Dynamic Phase Stepping feature enabled when targeting an Intel® MAX® 10 device. Resolution If using Dynamic Phase Stepping, implement the ALTPLL outside Platform Designer to avoid getting this error. This problem has been fixed in the Quartus II software v14.0