Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why do I get a fatal error when creating an ALTPLL IP?
Description Due to a problem in the Quartus® Standard Edition Software version 23.1, you might see a fatal error when creating an ALTPLL IP Using the MegaWizard Plug-In Manager. Resolution To work around this problem, download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1 Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Windows (.exe) Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Linux (.run) Readme for Quartus® Prime Standard Edition Software v23.1 Patch 0.02std (.txt) This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.How do I enable JTAG security in Intel® MAX® 10 devices?
Description An INI is required to enable the JTAG Security feature in Intel® MAX® 10 devices. Once the INI has been placed in your Intel® Quartus® Prime project directory, enable the option by accessing the MAX 10 Device options menu from the Convert Programming Files (CPF) settings. Note: when JTAG Secure mode is enabled, it will prevent any user access via the JTAG pins (which includes programming, examining, verifying, and erasing functions). In secure mode, the device will only accept SAMPLE/PRELOAD, BYPASS, EXTEXT, and IDCODE JTAG instructions. To unlock secure mode (for example to allow you to reprogram the device), you must implement an Intel MAX 10 JTAG atom (WYSIWYG type component) in the device that can be accessed only via the core. This will allow you to issue the JTAG UNLOCK instruction. See section 3.9 (titled Intel MAX 10 JTAG Secure Design Example) in the Intel MAX 10 FPGA Configuration User Guide for more information. Resolution Create a quartus.ini file with this setting: PGM_ENABLE_MAX10_JTAG_SECURITY=ON and place the file in your Intel Quartus Prime project directory. Access the ‘Enable JTAG security’ setting via File -> Convert programming files -> Options/Boot info (with configuration mode = internal).Do I need to drive fftpts_in of the FFT Intel® FPGA IP core even if I'm not changing the block size?
Description You may receive source errors (missing SOP, missing EOP) when attempting to process data through the FFT Intel® FPGA IP core when fftpts_in not being driven or being driven incorrectly. Resolution fftpts_in must be driven, even if one is not dynamically changing the block size. For a fixed block size implementation, it should be driven to match the transform length selected in the parameter editor.What timing constraints should I apply for the clock signal generated from the MAX®10 internal oscillator?
Description Depending on your configuration of the Max® internal oscillator, you should apply one of the two timing constraints below: For a Clock Frequency setting of 116MHz: create_clock -name test -period 116MHz [get_pins -compatibility {<path to instancve>|int_osc_0|oscillator_dut|clkout}] For a Clock Frequency setting of 55MHz: create_clock -name test -period 55MHz [get_pins -compatibility {<path to instancve>|int_osc_0|oscillator_dut|clkout}] Resolution This constraint will be automatically added in a future release of the Quartus® II software. This problem was fixed in Intel® Quartus® software version 15.0Why do I see hold time violations in the Intel® MAX® 10 FPGA On-Chip Flash in the Intel® Quartus® Prime Software version 15.1?
Description Due to a problem in the timing model in the Intel® Quartus® Prime Software version 15.1, you might see timing violations in the Intel MAX® 10 FPGA On-Chip Flash on the following register: *altera_onchip_flash_block:altera_onchip_flash_block|drdout[0] Note that this register is both the source and destination for the hold violation. Resolution This violation is false and can be ignored. This problem has been fixed in the Intel Quartus Prime Software v15.1.1Why do I observe different content in CFM and RPD files for Intel® MAX® 10 devices?
Description You might see a difference when comparing an RPD file generated by the Intel® Quartus® Prime Software and Intel® MAX® 10 device CFM contents. Resolution This is expected behavior due to bit-swapping during RPD file generation. An example of the purpose of bit swapping is described in Raw Programming Data File (.rpd) Definition.Error (14703): Invalid internal configuration mode for design with memory initialization
Description You may see this error while compiling a custom FIFO or a RAM block in the Intel® Quartus® Prime Software Standard or Lite versions for an Intel® MAX® 10 device. This error is seen because Intel® MAX® 10 device compact variants do not support memory initialization. If you have not provided any mif file for your custom design and still see this error in Intel® Quartus®Prime Edition Software, it may be because a mif file is being inferred by the RTL coding style Resolution Signal declaration for memory_type should be changed from signal mem : memory_type :=(others => (others => '0')); to signal mem : memory_type; This is to ensure that memory is not initialized and there is no compilation error in the Assembler stage.Internal Error: Sub-system: FIOMGR, File: /quartus/fitter/fiomgr/fiomgr_io_bank.cpp, Line: 2379 m_single_ended_iostd_drive_strength >= 0
Description Due to a problem in the Quartus® II software version 15.0 and earlier, you may see this internal error if you change the JTAG pin assignment from the default value. In MAX® 10 devices, JTAG pins are dual-purpose pins. If you use the JTAG pin as a dedicated pin, you do not need to do any pin assignment for the pin. You may get this internal error if you edit the pin assignment to anything other than the default value. Resolution To avoid the error, perform one of the following steps: Revert back all JTAG pin I/O standard to the default IO standard in the pin planner. Change to the default I/O standard to 3.3-V LVCMOS Go to Assignments -> Device -> Device and Pin Options -> Voltage -> change "Default I/O standard" to 3.3-V LVCMOSHow can I program the UFM with a hex/mif in Intel® MAX® 10 devices without impacting the CFM?
Description To program the User Flash Memory (UFM) with hex/mif in Intel® MAX® 10 devices without impacting the Configuration Flash Memory (CFM), do the following. Resolution Open the Convert Programming Files utility in Intel Quartus® Prime software Choose internal configuration in mode category. Go to Options/Boot info and select UFM source as load memory file. Choose a File path for your .hex or .mif file. After this process, add the SOF file to the main conversion window and generate *.pof file. Open Intel Quartus Prime Programmer. After proper recognition of the Intel MAX® 10 device, add the previously generated *.pof file and set Program / Configuration to UFM (only).