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Why is my Nios® II Simple Socket Server (RGMII) design example Ethernet link down when running on Intel FPGA Development Kits with MARVELL PHY?
Description Due to a problem in the Nios® II Software Build Tool, the default settings for the Nios® II Simple Socket Server (RMII) template are not targeted to MARVELL PHY. This resulted in wrong PHY...Why does the Arria® 10 Multi-Rate Ethernet PHY IP in USXGMII Auto-Negotiation mode fail in simulation?
Description The Arria® 10 Multi-Rate Ethernet PHY IP default value of usxgmii_link_timer at register address 0x412 is 0x7c000. This default reset value sets the link timer to 1.6ms, which is too l...120Views0likes0CommentsWhy is the timestamp accuracy error of the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Stratix® 10 FPGA IP with MGBASE-T Ethernet design higher than the expected value?
Description Due to a problem in the Quartus® Prime Pro Edition Software Version 22.3, Stratix® 10 PTP designs using the 1G/2.5G/5G/10G Multirate Ethernet PHY FPGA IP MGBASE-T variant may o...123Views0likes0CommentsWhy does my Intel® Arria® 10, 10G Multi-Rate Ethernet PHY - Lineside IP fail timing between the MAC and PHY on the TX datapath?
Description When using the Intel® Arria® 10, 10G Multi-rate Ethernet PHY - Lineside IP core, you may see hold timing violations for the data transfer from alt_mge16_phy_xcvr_term module to&n...127Views0likes0Comments10GBASE-R PHY IP Core Hold Time Violation in Arria V Ethernet MAC Example Design
Description The 10GBASE-R PHY IP Core has a hold time violation in the Arria V Ethernet MAC example design. This timing violation occurs for the fast model. Resolution The workaround is to add t...107Views0likes0CommentsHow do I set the Marvel 88E1111 Ethernet PHY on the Stratix IV E FPGA Development Kit to GMII mode?
Description The hardware default setting of Stratix® IV E FPGA Development Kit is incorrectly set to Serial Gigabit Media Independent Interface (SGMII) mode. The Marvel 88E1111 Ethernet PHY i...237Views0likes0Comments